Creating a thread of execution in a computer processor

• US 9,009,716 B2
• Filed: 04/27/2012
• Issued: 04/14/2015
• Est. Priority Date: 12/02/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bohrer, Patrick J., Gheith, Ahmed, Peterson, James L.
• Primary Examiner(s): ZHE, MENG YAO
• Application Number:
  US13/458,781
• Publication Number:
  US 20120216204A1
• Time in Patent Office: 1,082 Days
• Field of Search: None
• US Class Current: 718/103
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system

Abstract

Creating a thread of execution in a computer processor, including copying, as indicated by a hardware processor opcode having been specified by a user-level process, data from a first set of registers to a second set of registers, wherein the first set of registers is associated with a parent hardware thread, wherein the second set of registers is associated with a child hardware thread, wherein the child hardware thread is in a wait state, and changing, as indicated by the hardware processor opcode, the child hardware thread from the wait state to an ephemeral run state.

Claims

1. A method of creating a thread of execution in a computer processor, the method comprising:

copying, as indicated by a hardware processor opcode, the hardware processor opcode having been specified by a user-level process, data from a first set of registers to a second set of registers, wherein the first set of registers is associated with a parent hardware thread, wherein the second set of registers is associated with a child hardware thread, wherein the first set of registers and the second set of registers are located on the computer processor, wherein the child hardware thread is in a wait state; and

changing, as indicated by the hardware processor opcode, the child hardware thread from the wait state to an ephemeral run state, wherein the ephemeral run state indicates a lack of operating system support structures for the child hardware thread.

2. The method of claim 1 further comprising:

calling, by the child hardware thread, an operating system function; and

creating, by the operating system, a canonical operating system thread descriptor for the child hardware thread.

3. The method of claim 1 further comprising:

receiving, by the computer processor, an asynchronous interrupt of the child hardware thread thereby invoking an interrupt handler of the operating system; and

creating, by the operating system, a canonical operating system thread descriptor for the child hardware thread.

4. The method of claim 1 further comprising:

generate, by the child hardware thread, an execution exception that invokes an interrupt handler of the operating system; and

creating, by the operating system, a canonical operating system thread descriptor for the child hardware thread.

5. The method of claim 1, wherein the hardware processor opcode further comprises an operand specifying a maximum number of child hardware threads to change from the wait state to the ephemeral run state, the method further comprising:

returning, as indicated by the hardware processor opcode to the user-level process, a number of child hardware threads changed from the wait state to the ephemeral run state.

6. The method of claim 1 further comprising:

setting, as indicated by the hardware processor opcode for the parent hardware thread, a flag indicating whether any child hardware threads were changed from the wait state to the ephemeral run state.

7. The method of claim 1 further comprising:

setting, as indicated by the hardware processor opcode for the parent hardware thread, a flag identifying the parent hardware thread as a parent.

8. The method of claim 1, wherein said changing, as indicated by the hardware processor opcode, the child hardware thread from the wait state to an ephemeral run state further comprises setting a flag identifying the child hardware thread as a child hardware thread.

9. The method of claim 1, wherein said changing, as indicated by the hardware processor opcode, the child hardware thread from the wait state to an ephemeral run state further comprises assigning a unique thread identifier to the child hardware thread, wherein said assigning the unique thread identifier to the child hardware thread comprises storing an integer in a register of the child hardware thread.

10. The method of claim 1 further comprising:

returning, as indicated by a hardware processor opcode executed in the child hardware thread, the child hardware thread to the wait state.