Computer or microchip with a secure system BIOS and a secure control bus connecting a central controller to many network-connected microprocessors and volatile RAM

• US 9,009,809 B2
• Filed: 07/17/2014
• Issued: 04/14/2015
• Est. Priority Date: 01/26/2010
• Status: Active Grant

• Current Assignee: Frampton E. Ellis
• Original Assignee: Frampton E. Ellis
• Inventors: Ellis, Frampton E.
• Primary Examiner(s): SIMITOSKI, MICHAEL J
• Application Number:
  US14/333,759
• Publication Number:
  US 20140331305A1
• Time in Patent Office: 271 Days
• Field of Search: 726/11, 726/22, 726/30, 713/153, 713/154, 713/194
• US Class Current: 726/11
• CPC Class Codes: G06F 11/2043 where the redundant components share a common memory address space
• CPC Class Codes: G06F 21/50 Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/85 interconnection devices, e.g. bus-connected or in-line devices
• CPC Class Codes: H04L 63/02 for separating internal from external traffic, e.g. firewalls
• CPC Class Codes: H04L 63/0209 Architectural arrangements, e.g. perimeter networks or demilitarized zones

Abstract

A computer or microchip including a system BIOS located in flash memory which is located in a portion of the computer or microchip protected by an inner hardware-based access barrier or firewall, a central controller of the computer or microchip having a connection by a secure control bus with other parts of the computer or microchip, and a volatile random access memory located in a portion of the computer or microchip that has a connection for a network. The secure control bus is isolated from input from the network, and provides and ensures direct preemptive control by the central controller over the volatile random access memory, the control including transmission to or erasure of data and/or code in the volatile random access memory and control of a connection between the central controller, the volatile random access memory and at least one microprocessor having a connection for the network.

Claims

1. A computer or microchip, comprising:

a system BIOS of the computer or microchip located in flash memory which is located in a portion of the computer or microchip protected by an inner hardware-based access barrier or firewall; and

a central controller of the computer or microchip, including a master controlling device or a master control unit, having a connection by a secure control bus with other parts of the computer or microchip, and including at least a volatile random access memory (RAM) located in a portion of the computer or microchip that has at least one connection for a network;

the secure control bus is isolated from input from the network;

the secure control bus has a configuration by which it provides and ensures direct preemptive control by the central controller over the volatile random access memory (RAM);

the direct preemptive control includes transmission of data and/or code to the volatile random access memory (RAM) or erasure of data and/or code in the volatile random access memory (RAM); and

the direct preemptive control also includes control of a connection between the central controller and the volatile random access memory (RAM) and between the volatile random access memory (RAM) and at least one or many microprocessors having a connection for the network.

2. The computer or microchip according to claim 1, wherein said system BIOS further comprises a bus with an on/off switch controlling communication input and output.

3. The computer or microchip according to claim 2, wherein the secure control bus includes a first on/off switch that is located between the central controller and the volatile random access memory (RAM).

4. The computer or microchip according to claim 3, wherein the secure control bus includes a second on/off switch that is located between the volatile random access memory (RAM) and at least one said microprocessor having a connection for the network.

5. The computer or microchip according to claim 4, wherein the secure control bus has a configuration such the first on/off switch is closed and the second on/off switch is open, so that the central controller is connected to and has direct preemptive control over the volatile random access memory (RAM), which is disconnected from the network.

6. The computer or microchip according to claim 5, wherein the computer or microchip includes a public unit having a connection for the Internet and at least one private unit;

the central controller is located in said at least one private unit and the volatile random access memory (RAM) is located in the public unit.

7. The computer or microchip according to claim 6, wherein at least the first on/off switch is located in at least one other access barrier or firewall that is located between the public unit and the private unit.

8. The computer or microchip according to claim 7, wherein at least the volatile random access memory (RAM) is located in the at least one other access barrier or firewall that is located between the public unit and the private unit.

9. The computer or microchip according to claim 8, wherein at least the second on/off switch is located in the at least one other access barrier or firewall that is located between the public unit and the private unit.

10. The computer or microchip according to claim 5, wherein the central controller using the secure control bus is configured to erase the volatile random access memory (RAM).

11. The computer or microchip according to claim 10, wherein the central controller using the secure control bus is configured to erase the volatile random access memory (RAM) by power interruption to the volatile random access memory (RAM).

12. The computer or microchip according to claim 5, wherein the central controller using the secure control bus is configured to transmit data and/or code to the volatile random access memory (RAM).

13. The computer or microchip according to claim 4, wherein the secure control bus has a configuration such that the first on/off switch is open and the second on/off switch is closed, so that the volatile random access memory (RAM) is disconnected from the central controller and connected to the at least one said microprocessor having a connection for the network.

14. A computer or microchip, comprising:

a central controller of the computer or microchip, including a master controlling device or a master control unit;

a system BIOS of the computer or microchip located in flash memory;

a public unit including at least one network connection for a network and at least one private unit that is not connected to a network;

the central controller and the system BIOS are located in the at least one private unit;

at least one lock mechanism is located between the public unit and the at least one private unit and said at least one lock mechanism includes at least one volatile random access memory (RAM) and at least a first bus;

the at least a first bus includes at least a first on/off switch between the private unit and the at least one volatile random access memory (RAM) and at least a second on/off switch between the at least one volatile random access memory (RAM) and the public unit.

15. The computer or microchip according to claim 14, further comprising another bus with an on/off switch that controls communication input and output between the system BIOS and other parts of the computer or microchip.

16. The computer or microchip according to claim 15, wherein at least one access barrier or firewall is located between the public unit and the at least one private unit and said at least one access barrier or firewall separates the public unit from the at least one private unit, and includes the at least one lock mechanism.

17. The computer or microchip according to claim 16, wherein the lock mechanism has a configuration such that that the first on/off switch is closed and the second on/off switch is open, so that the central controller is connected to and has direct preemptive control over the volatile random access memory (RAM), which is disconnected from the public unit.

18. The computer or microchip according to claim 17, wherein the central controller using at least one said first bus is configured to erase the volatile random access memory (RAM).

19. The computer or microchip according to claim 18, wherein the central controller using at least one said first bus is configured to erase the volatile random access memory (RAM) by power interruption to the volatile random access memory (RAM).

20. The computer or microchip according to claim 17, wherein the central controller using at least one said first bus is configured to transmit data and/or code to the volatile random access memory (RAM).

21. The computer or microchip according to claim 16, wherein the secure control bus has a configuration such that that the first on/off switch is open and the second on/off switch is closed, so that the volatile random access memory (RAM) is disconnected from the central controller and connected to the public unit.

22. The computer or microchip according to claim 15, wherein the public unit includes at least one or many microprocessors.