Semiconductor device fabrication methods

• US 9,012,281 B2
• Filed: 03/14/2013
• Issued: 04/21/2015
• Est. Priority Date: 02/08/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Suk, Sung-Dae, Kang, Hee-Soo, Park, Sung-Il, Lee, Sang-Hoon
• Primary Examiner(s): Jahan, Bilkis
• Application Number:
  US13/829,703
• Publication Number:
  US 20140225198A1
• Time in Patent Office: 768 Days
• Field of Search: 257/197, 257/740, 257/238, 257/233, 257/300, 257/655, 257/682, 257/199, 257/561
• US Class Current: 438/233
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

Abstract

A semiconductor device includes a substrate having a first region and a second region, first and second gate electrodes disposed on the first and second regions, respectively, and first and second source/drain regions disposed on at least one side of the first and second gate electrodes, respectively. The device further includes first and second silicide regions in the first and second source/drain regions, respectively. A contact area between the first silicide region and the first source/drain region is differs in size from a contact area between the second silicide region and the second source/drain region. Methods of fabricating such devices are also provided.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

providing a substrate including a first region having a first gate electrode and a first source/drain region disposed adjacent the first gate electrode, and a second region having a second gate electrode and a second source/drain region disposed adjacent the second gate electrode;

forming an etch stop layer on the first and second source/drain regions of the first and second regions;

forming an interlayer insulating film on the etch stop layer;

etching the interlayer insulating film to expose portions of the etch stop layer in the first and second regions;

forming a resist layer on the second region;

etching the etch stop layer and an underlying portion of the first source/drain region in the first region using the resist layer as a mask to form a first contact hole having a first depth in the first source/drain region;

concurrently forming a first silicide region in the first contact hole and a sacrificial silicide region on the etch stop layer in the second region;

forming a second contact hole having a second depth different from the first depth in the second source/drain region by removing the sacrificial silicide region, a portion of the etch stop layer, and an underlying portion of the first source/drain region in the second region; and

forming a second silicide region in the second contact hole.

2. The method of claim 1, wherein the second silicide region and the third silicide region include different materials.

3. The method of claim 1, wherein the second contact hole is formed after forming the first silicide region, and wherein forming the second contact hole comprises etching the second source/drain region without using a resist layer on the first region while not etching a lower portion of the first contact hole.

4. The method of claim 1, wherein the method further comprises removing the resist layer after forming the first contact hole.