Semiconductor device including oxide semiconductor

• US 9,012,918 B2
• Filed: 03/24/2010
• Issued: 04/21/2015
• Est. Priority Date: 03/27/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Shishido, Hideaki, Abe, Takayuki
• Primary Examiner(s): Luu, Chuong A
• Assistant Examiner(s): ESKRIDGE, CORY W
• Application Number:
  US12/730,288
• Publication Number:
  US 20100244029A1
• Time in Patent Office: 1,854 Days
• Field of Search: None
• US Class Current: 257/72
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]

Abstract

The threshold voltage is shifted in a negative or positive direction in some cases by an unspecified factor in a manufacturing process of the thin film transistor. If the amount of shift from 0 V is large, driving voltage is increased, which results in an increase in power consumption of a semiconductor device. Thus, a resin layer having good flatness is formed as a first protective insulating film covering the oxide semiconductor layer, and then a second protective insulating film is formed by a sputtering method or a plasma CVD method under a low power condition over the resin layer. Further, in order to adjust the threshold voltage to a desired value, gate electrodes are provided over and below an oxide semiconductor layer.

Claims

1. A semiconductor device comprising:

a first gate electrode on an insulating surface;

a second gate electrode on the insulating surface;

a first gate insulating layer over the first gate electrode and the second gate electrode;

a first oxide semiconductor layer and a second oxide semiconductor layer each comprising indium, gallium, and zinc over the first gate insulating layer, wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer is a non-single-crystal semiconductor;

a first electrode layer and a second electrode layer over and in contact with the first oxide semiconductor layer, wherein one of the first electrode layer and the second electrode layer is electrically connected to the second oxide semiconductor layer and the second gate electrode;

a third electrode layer over and in contact with the second oxide semiconductor layer;

a second gate insulating layer over the first oxide semiconductor layer, the second oxide semiconductor layer, the first electrode layer, the second electrode layer and the third electrode layer;

a third gate electrode overlapping with the first oxide semiconductor layer with the second gate insulating layer interposed therebetween; and

a fourth gate electrode overlapping with the second oxide semiconductor layer with the second gate insulating layer interposed therebetween,

wherein the second gate insulating layer comprises a first insulating layer and a second insulating layer over the first insulating layer,

wherein the second insulating layer comprises one compound selected from the group consisting of silicon nitride, silicon oxynitride, and silicon nitride oxide,

wherein the first oxide semiconductor layer includes a region with a small thickness compared to a region of the first oxide semiconductor layer which overlaps with the first electrode layer or the second electrode layer,

wherein the second oxide semiconductor layer includes a region with a small thickness compared to a region of the second oxide semiconductor layer which overlaps with the third electrode layer,

wherein both the first gate electrode and the third gate electrode extend beyond side edges of the first oxide semiconductor layer in a channel width direction of the first oxide semiconductor layer, and

wherein both the second gate electrode and the fourth gate electrode extend beyond side edges of the second oxide semiconductor layer in a channel width direction of the second oxide semiconductor layer.

2. The semiconductor device according to claim 1,

wherein one of the first electrode layer and the second electrode layer is in direct contact with the second oxide semiconductor layer and the second gate electrode.

3. The semiconductor device according to claim 1, further comprising:

a first buffer layer between the first oxide semiconductor layer and the first electrode layer, and

a second buffer layer between the first oxide semiconductor layer and the second electrode layer.

4. The semiconductor device according to claim 1,

wherein the third gate electrode overlaps with the first oxide semiconductor layer and the first gate electrode.

5. The semiconductor device according to claim 1,

wherein a width of the third gate electrode is larger than a width of the first gate electrode in a channel length direction of the first oxide semiconductor layer.

6. The semiconductor device according to claim 1,

wherein a width of the first gate electrode is larger than a width of the first oxide semiconductor layer in a channel length direction of the first oxide semiconductor layer.

7. The semiconductor device according to claim 1, wherein the third gate electrode is in a floating state.

8. The semiconductor device according to claim 1, wherein the third gate electrode is a fixed potential of 0V.

9. The semiconductor device according to claim 1, wherein the first gate electrode and the third gate electrode have the same potential.

10. The semiconductor device according to claim 1, wherein a potential of the third gate electrode is configured to be fixed.

11. The semiconductor device according to claim 1, wherein the third gate electrode is electrically connected to the first gate electrode.

12. The semiconductor device according to claim 1 further comprising:

a cathode electrically connected to the first electrode layer or the second electrode layer;

a light-emitting layer over the cathode; and

an anode over the light-emitting layer.

13. The semiconductor device according to claim 1, wherein the first oxide semiconductor layer comprises silicon.