Adjustable field effect rectifier

• US 9,012,954 B2
• Filed: 02/16/2012
• Issued: 04/21/2015
• Est. Priority Date: 09/26/2007
• Status: Active Grant

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Ankoudinov, Alexei, Rodov, Vladimir
• Primary Examiner(s): Payen, Marvin
• Assistant Examiner(s): JOY, JEREMY J
• Application Number:
  US13/398,591
• Publication Number:
  US 20120211798A1
• Time in Patent Office: 1,160 Days
• Field of Search: 257/124, 257/133, 257/135, 257/328, 257/E29.066, 257/E29.257, 438/135, 438/138
• US Class Current: 257/124
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/861 Diodes

Abstract

An Adjustable Field Effect Rectifier uses aspects of MOSFET structure together with an adjustment pocket or region to result in a device that functions reliably and efficiently at high voltages without significant negative resistance, while also permitting fast recovery and operation at high frequency without large electromagnetic interference.

Claims

1. An apparatus comprising:

an epitaxial layer of a first conductivity and having first and second opposing sides;

a drain in said second side of said epitaxial layer;

a source in said first side of said epitaxial layer;

a gate dielectric layer on the first side of said epitaxial layer and being adjacent said source;

a gate contact layer on said gate dielectric layer;

said gate dielectric layer and said gate contact layer defining an opening therethrough;

a first well of the second conductivity in the epitaxial layer and being aligned with the opening;

an insulating layer in the opening and on said first well;

a second well of the second conductivity in the first side of said epitaxial layer, said second well being spaced apart from and having a depth greater than a depth of said first well;

a first electrically conductive contact coupled to the gate contact layer, and at least one of the first and second wells; and

a second electrically conductive contact coupled to the drain.

2. The apparatus of claim 1 further comprising an Ohmic contact adjacent said second well.

3. The apparatus of claim 1 wherein said insulating layer is configured to prevent current from passing through said epitaxial layer.

4. The apparatus of claim 3 wherein said insulating layer is configured to prevent current from passing through said epitaxial layer to said first well.

5. The apparatus of claim 1 wherein said gate dielectric layer comprises an oxide layer.

6. The apparatus of claim 1 wherein said gate dielectric layer extends over said first well.

7. The apparatus of claim 1 wherein said epitaxial layer defines first and second resistances between said source and said drain.

8. The apparatus of claim 1 wherein said epitaxial layer has a depth greater than the depth of said second well.

9. The apparatus of claim 1 further comprising a third well of the second conductivity in the first opposing side of said epitaxial layer for defining said source.