Semiconductor device and manufacturing method of the same

• US 9,013,006 B2
• Filed: 12/09/2013
• Issued: 04/21/2015
• Est. Priority Date: 05/20/2005
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Yatsuda, Yuji, Nakazawa, Yoshito
• Primary Examiner(s): Sun, Yu-Hsi D
• Assistant Examiner(s): SINGAL, ANKUSH K
• Application Number:
  US14/100,462
• Publication Number:
  US 20140193968A1
• Time in Patent Office: 498 Days
• Field of Search: 257/401
• US Class Current: 257/401
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for manufacturing a semiconductor device having a field-effect transistor, including forming a trench in a semiconductor substrate, forming a first insulating film in the trench, forming an intrinsic polycrystalline silicon film over the first insulating film, and introducing first conductive type impurities into the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. Next, a second insulating film is formed in the trench above the first insulating film and the first gate electrode, and

a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film, upper part of the trench ton form a second gate electrode.

Claims

1. A method for manufacturing a semiconductor device including a field-effect transistor, comprising steps of:

(a) forming a trench in a semiconductor substrate;

(b) forming a first insulating film in the trench;

(c) forming an intrinsic polycrystalline silicon film over the first insulating film;

(d) introducing impurities of a first conductivity type into the intrinsic polycrystalline silicon film to form a first conductive film;

(e) after the step (d), etching the first conductive film so as to provide a portion of the first conductive film in a lower part of the trench, thereby to form a first gate electrode of the field-effect transistor;

(f) forming a second insulating film in the trench, wherein the second insulating film is disposed above the first insulating film and the first gate electrode;

(g) forming a doped polycrystalline silicon film of the first conductivity type, having higher impurity concentration than the first gate electrode, over the second insulating film; and

(h) etching the doped polycrystalline silicon film so as to provide a portion of the doped polycrystalline silicon film in an upper part of the trench, thereby to form a second gate electrode of the field-effect transistor.

2. A method for manufacturing a semiconductor device according to the claim 1,

wherein, at the step (e), a first lead-out part of the first gate electrode is formed in an outer peripheral portion of the trench and is electrically connected to the first gate electrode, and

wherein, at the step (h), a second lead-out part of the second gate electrode is formed in the outer peripheral portion of the trench and is electrically connected to the second gate electrode.

3. A method for manufacturing a semiconductor device according to the claim 2,

wherein a thickness of the first lead-out part is smaller than a thickness of the second lead-out part.

4. A method for manufacturing a semiconductor device according to the claim 1,

wherein a thickness of the first insulating film is larger than a thickness of the second insulating film.

5. A method for manufacturing a semiconductor device according to the claim 1, further comprising forming the first insulating film by a thermal oxidation process.

6. A method for manufacturing a semiconductor device according to the claim 1, further comprising forming the second insulating film by a thermal oxidation process.

7. A method for manufacturing a semiconductor device according to the claim 1, further comprising, at the step (g), forming the doped polycrystalline silicon film by a CVD method.

8. A method for manufacturing a semiconductor device according to the claim 1,

wherein the first conductivity type is n-type conductivity.

9. A method for manufacturing a semiconductor device including a field-effect transistor, comprising steps of:

(a) forming a trench in a semiconductor substrate;

(b) forming a first gate electrode of the field-effect transistor in the trench; and

(c) forming a second gate electrode of the field-effect transistor in the trench and over the first gate electrode,

wherein the step (b) includes steps of forming an intrinsic polycrystalline silicon film in the trench and introducing impurities into the intrinsic polycrystalline silicon film,

wherein the step (c) includes a step of forming a doped polycrystalline silicon film in the trench by a CVD method, and

wherein an impurity concentration of the first gate electrode is lower than an impurity concentration of the second gate electrode.

10. A method for manufacturing a semiconductor device according to the claim 9,

wherein a first lead-out part of the first gate electrode is formed in an outer peripheral portion of the trench and is electrically connected to the first gate electrode, and

wherein a second lead-out part of the second gate electrode is formed in the outer peripheral portion of the trench and is electrically connected to the second gate electrode.

11. A method for manufacturing a semiconductor device according to the claim 10,

wherein a thickness of the first lead-out part is smaller than a thickness of the second lead-out part.

12. A method for manufacturing a semiconductor device according to the claim 9,

wherein a thickness of the first insulating film is larger than a thickness of the second insulating film.

13. A method for manufacturing a semiconductor device according to the claim 9, further comprising forming the first insulating film is formed by a thermal oxidation process.

14. A method for manufacturing a semiconductor device according to the claim 9,

wherein the second insulating film is formed by a thermal oxidation process.

15. A method for manufacturing a semiconductor device according to the claim 9,

wherein the first and second gate electrode are an n-type, respectively.