×

Circuits for improving linearity of metal oxide semiconductor (MOS) transistors

  • US 9,013,226 B2
  • Filed: 09/26/2012
  • Issued: 04/21/2015
  • Est. Priority Date: 09/26/2012
  • Status: Active Grant
First Claim
Patent Images

1. A circuit for improving linearity of a Metal Oxide Semiconductor (MOS) transistor comprising a gate, a source and a drain, the circuit comprising:

  • an averaging circuit configured to provide a signal at the gate in response to signals at the drain and the source, the averaging circuit comprising;

    a first MOS circuit configured to be coupled between the drain and the gate, wherein the first MOS circuit comprises;

    a source follower MOS circuit comprising;

    a first PMOS transistor having a gate node coupled with the drain of the MOS transistor, anda first current source coupled between a power supply and a source node of the first PMOS transistor; and

    a first resistor coupling the source node of the first PMOS transistor with the gate of the MOS transistor, anda second MOS circuit configured to be coupled between the source and the gate; and

    one or more current sources coupled with the gate, the one or more current sources configured to vary currents in the first and second MOS circuits so as to vary a voltage at the gate and thereby vary a resistance of the MOS transistor.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×