Inrush current control circuit and method for utilizing same

• US 9,013,851 B2
• Filed: 02/22/2010
• Issued: 04/21/2015
• Est. Priority Date: 02/22/2010
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Kidd, David Anthony, Senthinathan, Ramesh
• Primary Examiner(s): Tran, Thienvu
• Assistant Examiner(s): CLARK, CHRISTOPHER JAY
• Application Number:
  US12/660,232
• Publication Number:
  US 20110205680A1
• Time in Patent Office: 1,884 Days
• Field of Search: 361/93.9, 361/93.1, 361/93.2
• US Class Current: 361/93.9
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: H03K 17/164 using parallel switching arrangements

Abstract

Disclosed is an inrush current control circuit for controlling current into a high-current circuit block. The inrush current control circuit comprises a number of distributed switches and a digital control circuit coupled to at least one of the distributed switches. The digital control circuit is configured to switch a first group of the distributed switches in response to an enable/disable signal. The digital control circuit is further configured to switch a second group of the distributed switches after a first programmable delay. According to one embodiment, a method comprises switching a first group of distributed switches by a digital control circuit of an inrush current control circuit in response to an enable/disable signal, and switching a second group of the distributed switches by the digital control circuit after a first programmable delay, thereby resulting in regulation of a flow of an inrush current.

Claims

1. A current control circuit for controlling and regulating current into a high-current circuit block, comprising:

a plurality of switched-power cells disposed in the high-current circuit block, each of the plurality of switched-power cells including

a high-current circuit, and

a switch configured to connect the high-current circuit to a power source; and

a digital control circuit coupled to each switch of the plurality of switched-power cells and configured to;

turn on switches of a first group of said plurality of switched-power cells in response to an enable/disable signal to power the first group of the switched-power cells, and

turn on switches of a second group of switched-power cells after a first programmable delay to power the second group of the switched-power cells,

wherein at least one switched-power cell of the second group of switched power cells is situated between two switched power cells of the first group of switched-power cells.

2. The current control circuit of claim 1, wherein said current control circuit is configured to activate a state of said high-current circuit block.

3. The current control circuit of claim 1, wherein said digital control circuit is further configured to turn on switches of a third group of switched-power cells after a second programmable delay to power the third group of switched-power cells to the power source.

4. The current control circuit of claim 3, wherein said first programmable delay is not equal to said second programmable delay.

5. The current control circuit of claim 1, wherein said digital control circuit further comprises at least one isolation cell to prevent a crowbar current from flowing between said current control circuit and said high-current circuit block.

6. The inrush current control circuit of claim 1, wherein each of the first group of switched-power cells is laid out in a different column of switched-power cells than switched-power cells of the second group of switched power cells.

7. The current control circuit of claim 1, wherein said current control circuit is configured to deliver an analog voltage to the switch in each of the plurality of switched-power cells.

8. The current control circuit of claim 1, wherein the switch in each of said plurality of switched-power cells comprises a power gate.

9. The current control circuit of claim 1, wherein the switch in each of said plurality of switched-power cells comprises a P type metal-oxide semiconductor (“

PMOS”

) header transistor.

10. The current control circuit of claim 9, further comprising a well tie connecting a well of said PMOS header transistor to a power supply.

11. The current control circuit of claim 1, further comprising a substrate tie connecting a substrate of said current control circuit to the power source.

12. The current control circuit of claim 1, wherein said current control circuit and said high-current circuit block are situated on one semiconductor die.

13. A method for use by a current control circuit for regulating a flow of current in a high-current circuit block including switched-power cells, comprising:

turning on switches of a first group of switched-power cells by a digital control circuit of said current control circuit and in response to an enable/disable signal, to power the first group of switched-power cells, the switches of the first group of switched-power cells connecting the first group of switched-power cells to a power source; and

turning on switches of a second group of switched power cells by said digital control circuit after a first programmable delay to regulate flow of the current, the switches of the second group of switched-power cells connecting the second group of switched-power cells to the power source;

wherein at least one switched-power cell of the second group of switched-power cells is situated between two switched-power cells of the first group of switched-power cells.

14. The method of claim 13, further comprising turning on switches of a third group of switched-power cells by said digital control circuit after a second programmable delay, the switches of the third group of switched-power cells connecting the third group of switched-power cells to the power source.

15. The method of claim 13, further comprising changing a state of said high-current circuit block.

16. The method of claim 13, further comprising preventing a crowbar current from passing from said high-current circuit block.

17. A current control circuit for activating a high-current circuit block, comprising:

a plurality of switched-power cells included in the high-current circuit block, each of the plurality of switched-power cells including

a high-current circuit, and

a switch configured to connect the high-current circuit to a power source; and

a digital control circuit coupled to the switch of each of the plurality of switched-power cells and configured to;

turn on switches of a first group of the switched-power cells in response to an enable/disable signal to power the first group of the switched-power cells,

turn on switches of a second group of the switched-power cells after a first programmable delay to power the second group of the switched-power cells, and

turn on switches of a third group of the switched-power cells after a second programmable delay to power the third group of the switched-power cells,

wherein at least one switched-power cell of the second group of switched power cells is situated between two switched power cells of the first group of switched-power cells.

18. The current control circuit of claim 17, wherein the switch of each of the plurality of switched-power cells comprises a P type metal-oxide semiconductor (“

PMOS”

) header transistor.

19. The current control circuit of claim 18, further comprising a well tie connecting a well of said PMOS transistor to the power source.

20. The current control circuit of claim 17, wherein said digital control circuit further comprises at least one isolation cell to prevent a crowbar current from flowing between said current control circuit and said high-current circuit block.