Multiplierless coprocessor for difference of Gaussian (DoG) calculation

• US 9,014,508 B2
• Filed: 04/24/2013
• Issued: 04/21/2015
• Est. Priority Date: 04/24/2012
• Status: Expired due to Fees

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Vigliar, Mario, Licciardo, Gian Domenico
• Primary Examiner(s): Wu, Jingge
• Application Number:
  US13/869,665
• Publication Number:
  US 20130301950A1
• Time in Patent Office: 727 Days
• Field of Search: None
• US Class Current: 382/303
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 5/50 using two or more images, e.g. averaging or subtraction
• CPC Class Codes: G06T 5/73 Deblurring; Sharpening

Abstract

A hardware architecture is applied to the calculation of a Difference-of-Gaussian filter, which is typically employed in image processing algorithms. The architecture has a modular structure to easily allow the matching of the desired delay/area ratio as well as a high computational accuracy. A new solution is provided for the implementation of multiply-accumulators which allows a significant reduction of area with respect to the conventional architectures.

Claims

1. A multiplier accumulator circuit comprising:

a first lookup table configured to provide Bachet terms in response to an input pixel value;

a plurality of second lookup tables configured to provide intermediate values in response to the Bachet terms; and

a set of full adders configured to sum the inte mediate values from the second lookup tables and to provide an output value representative of the input pixel value multiplied by a coefficient.

2. A multiplier accumulator circuit as defined in claim 1, wherein the set of full adders is configured to add a further input value to the output value representative of the input pixel value multiplied by the coefficient.

3. A multiplier accumulator circuit as defined in claim 1, configured for use in a Difference-of-Gaussian calculation, wherein the coefficient is a Gaussian coefficient.

4. A multiplier accumulator circuit as defined in claim 1, wherein the input pixel value is an eight-bit data value.

5. A multiplier accumulator circuit as defined in claim 1, wherein the plurality of second lookup tables includes six second lookup tables and wherein the set of full adders includes five full adders.

6. A multiplier accumulator circuit as defined in claim 2, wherein the plurality of second lookup tables includes six second lookup tables and wherein the set of full adders includes six full adders.

7. A multiply accumulate method comprising:

providing Bachet terms from a first lookup table in response to an input pixel value;

providing intermediate values from a plurality of second lookup tables in response to the Bachet terms; and

summing the intermediate values with a set of full adders to provide an output value representative of the input pixel value multiplied by a coefficient.

8. A multiply accumulate method as defined in claim 7, further comprising adding a further input value to the output value representative of the input pixel value multiplied by the coefficient.

9. A multiply accumulate method as defined in claim 7, used in a Difference-of-Gaussian calculation, wherein the coefficient is a Gaussian coefficient.