Adaptable datapath for a digital processing system

• US 9,015,352 B2
• Filed: 03/31/2014
• Issued: 04/21/2015
• Est. Priority Date: 03/22/2001
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Ramchandran, Amit
• Primary Examiner(s): Lee, Chun-Kuan
• Assistant Examiner(s): LEWIS-TAYLOR, DAYTON A.
• Application Number:
  US14/230,529
• Publication Number:
  US 20140215180A1
• Time in Patent Office: 386 Days
• Field of Search: None
• US Class Current: 710/4
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/287 Multiplexed DMA G06F13/30 takes precedence
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., Discrete Cosine Transform (DCT), Fast-Fourier Transform (FFT) and other operations. Other features are provided.

Claims

1. A reconfigurable data path circuit coupled to a memory bus for obtaining data from a memory, the reconfigurable data path circuit comprising:

a functional unit configured to perform a digital operation;

one or more multiplexers coupled to the memory bus;

a configurable data path configurably coupled to the one or more multiplexers and the functional unit, the configurable data path configured in response to a first configuration information to provide a data path configuration by configuring interconnections between the one or more multiplexers and the functional unit;

wherein the one or more multiplexers are coupled to the memory bus and the configurable data path, each of the one or more multiplexers configured in response to a second configuration information that is different from the first configuration information to generate memory addresses from which data is to be read from or written to the memory for the data path configuration.

2. The reconfigurable data path circuit of claim 1, wherein the configuration information includes a context field including context information describing a predetermined configuration for the reconfigurable data path circuit.

3. The reconfigurable data path circuit of claim 2, wherein the one or more multiplexers are further configurable or reconfigurable in response to the second configuration information to read data of one or more widths from the memory bus consistent with and for the data path configuration and the context information.

4. The reconfigurable data path circuit of claim 3, wherein the one or more multiplexers transfer data to the configurable data path for processing by the functional units in parallel.

5. The reconfigurable data path circuit of claim 2, wherein at least one of the plurality of functional units is configurable to provide at least two different functions, the at least two different functions being selectable based on the context information.

6. The reconfigurable data path circuit of claim 1, wherein the first and second configuration information each comprises a separate control word.

7. The reconfigurable data path circuit of claim 6, wherein each separate control word includes an operation field.

8. The reconfigurable data path circuit of claim 7, wherein each control word further comprises an address field, the address field designating one of the memory addresses.

9. The reconfigurable data path circuit of claim 1, wherein the one or more multiplexers are configurable in response to the second configuration information to split data received from the memory bus onto the configurable data path.

10. The reconfigurable data path circuit of claim 1, wherein each of the functional units of the plurality of functional units include one of a multiplier, an accumulator, a data cache, an Arithmetic Logic Unit (ALU), or a register.

11. The reconfigurable data path circuit of claim 1, further comprising a plurality of register files each configurably interconnected by the configurable data path to the plurality of functional units and to one of the one or more multiplexers.

12. The reconfigurable data path circuit of claim 1, wherein the configurable data path further comprises a reconfigurable interconnection network configurable for configuring or reconfiguring the interconnections between or among the one or more multiplexers and the plurality of functional units for the data path configuration.

13. The reconfigurable data path circuit of claim 12, wherein the reconfigurable interconnection network includes a plurality of groups of data lines configurably coupled to the one or more multiplexers and the plurality of functional units.

14. The reconfigurable data path circuit of claim 12, wherein the reconfigurable interconnection network is configurable or reconfigurable to create portions of the reconfigurable data paths having different widths, the portions being coupled between the data address generators and the plurality of functional units.

15. The reconfigurable data path circuit of claim 12, wherein the plurality of functional units are configurable to provide a second plurality of configurable data paths between respective ones of the plurality of functional units and the reconfigurable interconnection network.

16. The reconfigurable data path circuit of claim 15, wherein the second plurality of configurable data paths are configurable for a plurality of data widths.

17. The reconfigurable data path circuit of claim 1, wherein the interconnections of the configurable data path and the one or more multiplexers are configurable in real time.

18. A digital processing system comprising:

a memory bus coupled to a memory; and

a reconfigurable data path circuit coupled to the memory bus for obtaining data from the memory, the reconfigurable data path circuit comprising;

a plurality of functional units configurable to perform a digital processing operation; and

one or more multiplexers coupled to the memory bus;

a configurable data path configurably coupled to the one or more multiplexers and the plurality of functional units, the configurable data path being configurable in response to a first configuration information to provide a data path configuration by configuring or reconfiguring interconnections between or among the one or more multiplexers and the plurality of functional units, the data path configuration including the configured or reconfigured interconnections, the one or more data address generators being coupled between the memory bus and the configurable data path, each of the one or more multiplexers being configurable in response to a second configuration information to generate memory addresses from which data is to be read from or written to the memory consistent with and for the data path configuration.

19. The digital processing system of claim 18, further comprising a plurality of register files each configurably interconnected by the configurable data path to the plurality of functional units and to one of the one or more multiplexers.

20. A method for generating memory addresses for obtaining data from a memory using a reconfigurable data path circuit coupled to a memory bus, the reconfigurable data path circuit comprising a functional unit configured to perform a digital operation, one or more data address generators coupled to the memory bus, a configurable data path configurably coupled to the one or more data address generators and the functional unit, the method comprising:

providing a first configuration information to configure the configurable data path to provide a data path configuration by configuring interconnections between the one or more data address generators and the functional unit, whereby the one or more data address generators are coupled to the memory bus and the configurable data path;

providing a second configuration information, said second configuration information being different from the first configuration information to each of the one or more data address generators and

generating memory addresses from which data is to be read from or written to the memory for the data path configuration in response to the second configuration information.