Active memory data compression system and method

• US 9,015,390 B2
• Filed: 04/25/2003
• Issued: 04/21/2015
• Est. Priority Date: 04/25/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Klein, Dean A.
• Primary Examiner(s): Park, Ilwoo
• Application Number:
  US10/424,206
• Publication Number:
  US 20040215852A1
• Time in Patent Office: 4,379 Days
• Field of Search: 710/5, 710/68, 712/16, 712 20- 22, 712/11, 712/14
• US Class Current: 710/68
• CPC Class Codes: G06F 15/7821 Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
• CPC Class Codes: G06F 15/785 with decentralized control, e.g. smart memories
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]

Abstract

An integrated circuit active memory device receives task commands from a component in a host computer system that may include the active memory device. The host system includes a memory controller coupling the active memory device to a host CPU and a mass storage device. The active memory device includes a command engine issuing instructions responsive to the task commands to either an array control unit or a DRAM control unit. The instructions provided to the DRAM control unit cause data to be written to or read from a DRAM and coupled to or from either the processing elements or a host/memory interface. The processing elements execute instructions provided by the array control unit to decompress data written to the DRAM through the host/memory interface and compress data read from the DRAM through the host/memory interface.

Claims

1. An integrated circuit active memory device comprising:

a memory device having a data bus containing a plurality of data bus bits;

an array of processing elements each of which is coupled to a respective group of the data bus bits, each of the processing elements having an instruction input coupled to receive processing element instructions for controlling the operation of the processing elements;

register files coupled to the array of processing elements and the memory device, the register files transferring data between the processing elements and the memory device;

a host interface port coupled to the memory device and operable to receive direct access memory commands to provide direct access to the memory device to transfer compressed data to and from the memory device;

a task buffer coupled to a command engine and a memory controller, the task buffer operable to receive high level task commands from the memory controller and provide the high level commands to the command engine in an order received, wherein the high level task commands include a task address;

the command engine coupled to receive task commands from the task buffer and operable to generate corresponding sequences of processing element instructions and memory instructions responsive to respective task commands to control the operation of the memory device and the processing elements to generate corresponding sequences of instructions to read data from and write data to the memory device, at least some of the instructions generated by the command engine responsive to the task commands causing the processing elements to decompress compressed data transferred to the active memory device through the host interface port and store the decompressed data in the memory device or to compress decompressed data transferred from the memory device that is to be transferred from the active memory device through the host interface port;

a processing element instructions buffer coupled to the command engine and an array control unit, the processing element instructions buffer operable to receive sequences of processing element instructions from the command engine and provide the sequences of processing element instructions to the array control unit in an order received;

the array control unit coupled to the processing element instructions buffer and the processing elements, the array control unit being operable to receive the sequences of processing element instructions from the processing element instructions buffer and to generate array control unit microinstructions responsive to the sequences of processing element instructions received from the processing element instructions buffer, at least some of the microinstructions causing the processing elements to either decompress data transferred to the active memory device through the host interface port and then store the decompressed data in the memory device or to compress decompressed data transferred from the memory device that is to be transferred through the host interface port;

a memory instructions buffer coupled to the command engine and a memory device control unit, the memory instructions buffer operable to receive sequences of memory instructions from the command engine and provide the sequences of memory instructions to the memory device in an order received; and

the memory device control unit coupled to the memory instructions buffer and the memory device, the memory device control unit operable to receive the sequences of memory instructions from the memory instructions buffer and to generate memory commands responsive to the sequences of memory instructions received from the memory instructions buffer.

2. The active memory device of claim 1 wherein the memory device comprises a dynamic random access memory device.

3. The active memory device of claim 1 wherein a host interface port is operable to transfer data to and from the memory device before the transferred data is decompressed and compressed, respectively, by the processing elements.

4. The active memory device of claim 1 further comprising

a program memory coupled to the array control unit and configured to store a plurality of intrinsics each of which includes a plurality of microinstructions that are executed by the processing elements, the program memory being addressed by the array control unit, at least one of the intrinsics causing the processing elements to decompress data transferred to the active memory device through the host interface port and at least another of the intrinsics causing the processing elements to compress data transferred from the memory device.

5. The active memory device of claim 1 wherein the host interface port is coupled to the memory control unit to supply control signals the memory control unit, the memory control unit applying control signals to the memory device responsive to control signals received from the host interface port.

6. The active memory device of claim 1 wherein the processing elements comprise single instruction, multiple data processing elements that receive common instructions from the control unit.

7. The active memory device of claim 1 wherein the processing elements comprise multiple instruction, multiple data processing elements at least some of which receive instructions from the control unit that are different from instructions received from the control unit by other of the processing elements.

8. The active memory device of claim 1, further comprising a program memory storing a plurality of intrinsics each of which includes a plurality of microinstructions that are executed by the processing elements, the program memory being addressed by the array control unit, at least one of the intrinsics causing the processing elements to decompress data transferred to the active memory device through the host interface port and at least another of the intrinsics causing the processing elements to compress data transferred from the memory device.

9. A computer system, comprising:

a host processor;

a peripheral device coupled to the host processor;

a memory controller coupled to the host processor and the peripheral device; and

an integrated circuit active memory device, comprising;

a memory device having a data bus containing a plurality of data bus bits;

an array of processing elements each of which is coupled to a respective group of the data bus bits, each of the processing elements having an instruction input coupled to receive processing element instructions for controlling the operation of the processing elements;

register files coupled to the array of processing elements and the memory device, the register files transferring data between the processing elements and the memory device;

a host/memory interface coupled to the memory controller and coupled to the memory device, the host/memory interface being operable to receive direct access memory commands to provide direct access to the memory device to transfer compressed data to or from the peripheral device and the active memory device;

a task buffer coupled to the memory controller and a command engine, the task buffer operable to receive high level task commands from the memory controller and provide the high level commands to the command engine in an order received, wherein the high level task commands include a task address;

a command engine coupled to the task buffer, the command engine being operable to receive task commands from the task buffer and operable to generate corresponding sequences of processing element instructions and memory instructions responsive to respective task commands to control the operation of the memory device and the processing elements to generate corresponding sequences of instructions responsive to memory commands to read data from and write data to the memory device, at least some of the instructions generated by the command engine responsive to the task commands causing the processing elements to decompress compressed data transferred to the active memory device through the host interface port and store the decompressed data in the memory device or to compress decompressed data read from the memory device, and to transfer the compressed data from the active memory device through the host interface port;

a processing element instructions buffer coupled to the command engine and an array control unit, the processing element instructions buffer operable to receive sequences of processing element instructions from the command engine and provide the sequences of processing element instructions to the array control unit in an order received;

the array control unit coupled to the processing element instructions buffer and the processing elements, the array control unit being operable to receive sequences of processing element instructions from the processing element instructions buffer and to generate array control unit microinstructions responsive to the sequences of processing element instructions received from the processing element instructions buffer, at least some of the microinstructions causing the processing elements to either decompress data transferred from the peripheral literal device to the active memory device through the host interface/memory interface and then store the decompressed data in the memory device or to compress previously decompressed data transferred from the memory device that is to be transferred to the peripheral device through the host/memory interface;

a memory instructions buffer coupled to the command engine and a memory device control unit, the memory instructions buffer operable to receive sequences of memory instructions from the command engine and provide the sequences of memory instructions to the memory device in an order received; and

the memory device control unit coupled to the memory instructions buffer and the memory device, the memory device control unit operable to receive sequences of memory instructions from the memory instructions buffer and to generate memory commands responsive to the sequences of memory instructions received from memory instructions buffer.

10. The computer system of claim 9 wherein the memory device comprises a dynamic random access memory device.

11. The computer system of claim 9 wherein the peripheral device comprises a mass storage device.

12. The computer system of claim 11 wherein the mass storage device comprises a disk drive unit.

13. The computer system of claim 9 wherein a host/memory interface is operable to transfer data to and from the memory device before the transferred data is decompressed and compressed, respectively, by the processing elements.

14. The computer system of claim 9 further comprising

a program memory coupled to the array control unit and configured to store a plurality of intrinsics each of which includes a plurality of microinstructions that are executed by the processing elements, the program memory being addressed by the array control unit, at least one of the intrinsics causing the processing elements to decompress data transferred to the active memory device through the host/memory interface and at least another of the intrinsics causing the processing elements to compress data transferred from the memory device.

15. The computer system of claim 9 wherein the host/memory interface is coupled to the memory control unit to supply control signals the memory control unit, the memory control unit applying control signals to the memory device responsive to control signals received from the host/memory interface.

16. The computer system of claim 9 wherein the processing elements comprise single instruction, multiple data processing elements that receive common instructions from the control unit.

17. The computer system of claim 9 wherein the processing elements comprise multiple instruction, multiple data processing elements at least some of which receive instructions from the control unit that are different from instructions received from the control unit by other of the processing elements.

18. The computer system of claim 12 a program memory storing a plurality of intrinsics each of which includes a plurality of microinstructions that are executed by the processing elements, the program memory being addressed by the array control unit, at least one of the intrinsics causing the processing elements to decompress data transferred to the active memory device through the host/memory interface and at least another of the intrinsics causing the processing elements to compress data transferred from the memory device.

19. The computer system of claim 9, further comprising a plurality of active memory devices coupled to the memory controller, each of the plurality of active memory devices comprising:

a memory device having a data bus containing a plurality of data bus bits;

an array of processing elements each of which is coupled to a respective group of the data bus bits, each of the processing elements having an instruction input coupled to receive processing element instructions for controlling the operation of the processing elements;

a host/memory interface coupled to the memory controller, the host/memory interface being operable to transfer data to or from the peripheral device and the active memory device; and

a control unit coupled to the memory controller, the control unit being operable to receive task commands from the memory controller and to generate corresponding sequences of instructions responsive to each of the task commands to control the operation of the memory device and the processing elements, at least some of the instructions generated by the control unit causing the processing elements to either decompress data transferred to the active memory device through the host interface port and then store the decompressed data in the memory device or to compress data transferred from the memory device that is to be transferred from the active memory device through the host interface port; and

wherein the memory controller is operable to sequentially transfer data to and from each of the plurality of active memory devices through the respective memory/host interface of the memory devices.

20. A computer system, comprising:

a host processor;

a peripheral device coupled to the host processor;

a memory controller coupled to the host processor and the peripheral device; and

an integrated circuit active memory device, comprising;

a task command interface coupled to the memory controller and configured to receive task commands, wherein the task commands include a task address, and wherein the task command interface is a first-in, first-out buffer and provides the task commands in an order received;

a host/memory interface coupled to the memory controller, the host/memory interface being operable to transfer data to or from the peripheral device and the active memory device;

a processor operable to decompress compressed data that has been transferred to the active memory device through the host/memory interface and to compress the uncompressed data to be transferred through the host/memory interface from the active memory device;

a memory device coupled to the processor, the memory device being operable to store uncompressed data and compressed data;

register files coupled to the processor and the memory device, the register files configured to provide compressed data from the memory device to the processor to be decompressed and further configured to provide uncompressed data from the memory device to the processor to be compressed;

a task command engine coupled to the task command interface and operable to generate processing instructions for the processor and memory instructions for the memory device responsive to respective task commands including the task address;

a processing instructions buffer coupled to the task command engine and an array control unit, the processing instruction buffer operable to receive the processing instructions from the task command engine and provide the processing instructions to the array control unit in an order received;

the array control unit coupled to the task command engine and processor, the array control unit operable to receive the processing instructions from the processing instructions buffer and to generate microinstructions responsive to the processing instructions received from the processing instructions buffer and provide the microinstructions to the processor, at least some of the microinstructions causing the processor to either decompress compressed data transferred from the memory device or to compress uncompressed data transferred from the memory device;

a memory instructions buffer coupled to the task command engine and a memory device, the memory instructions buffer operable to receive the memory instructions from the task command engine and provide the memory instructions to the memory device in an order received; and

the memory device control unit coupled to the memory instructions buffer and the memory device, the memory device control unit operable to receive memory instructions from the memory instructions buffer and to generate memory commands responsive to the memory instructions received from the memory instructions buffer.

21. The computer system of claim 20 wherein the processor comprises a plurality of processing elements each of which is coupled to a group of data bus bits of the memory device.

22. The computer system of claim 21 wherein the processing elements comprise single instruction, multiple data processing elements.

23. The computer system of claim 21 wherein the processing elements comprise multiple instruction, multiple data processing elements.

24. The computer system of claim 20 wherein the memory device comprises a dynamic random access memory device.

25. The computer system of claim 20 wherein a host interface port is operable to transfer data to and from the memory device before the transferred data is decompressed and compressed, respectively, by the processor.