Reducing remote reads of memory in a hybrid computing environment

• US 9,015,443 B2
• Filed: 04/30/2010
• Issued: 04/21/2015
• Est. Priority Date: 04/30/2010
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Aho, Michael E., Archer, Charles J., Carey, James E., Markland, Matthew W., Sanders, Philip J.
• Primary Examiner(s): Rones, Charles
• Assistant Examiner(s): DARE, RYAN A
• Application Number:
  US12/771,627
• Publication Number:
  US 20110271059A1
• Time in Patent Office: 1,817 Days
• Field of Search: None
• US Class Current: 711/170
• CPC Class Codes: G06F 9/3881 Arrangements for communication of instructions and data
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes

Abstract

A hybrid computing environment in which the host computer allocates, in the shadow memory area of the host computer, a memory region for a packet to be written to the shared memory of an accelerator; writes packet data to the accelerator'"'"'s shared memory in a memory region corresponding to the allocated memory region; inserts, in a next available element of the accelerator'"'"'s descriptor array, a descriptor identifying the written packet data; increments the copy of the head pointer of the accelerator'"'"'s descriptor array maintained on the host computer; and updates a copy of the head pointer of the accelerator'"'"'s descriptor array maintained on the accelerator with the incremented copy.

Claims

1. A method of reducing remote reads of memory in a hybrid computing environment, the hybrid computing environment comprising a host computer having a host computer architecture, a plurality of accelerators having an accelerator architecture, the accelerator architecture optimized, with respect to the host computer architecture, for speed of execution of a particular class of computing functions, the host computer and the accelerators adapted to one another for data communications by a system level message passing module, the host computer having local memory shared remotely with the accelerators and having a shadow memory area, each accelerator having local memory shared remotely with the host computer, each accelerator comprising a descriptor array, the descriptor array comprising a plurality of elements, each element of the descriptor array capable of storing a descriptor identifying packet data to be read from the accelerator'"'"'s shared memory, the method comprising:

allocating, by the host computer in the shadow memory area of the host computer, a memory region for a packet to be written to the shared memory of an accelerator;

writing packet data by the host computer to the accelerator'"'"'s shared memory in a memory region corresponding to the allocated memory region in the host computer'"'"'s shadow memory area;

inserting, by the host computer in a next available element of the accelerator'"'"'s descriptor array, a descriptor identifying the written packet data including identifying the next available element of the accelerator'"'"'s descriptor array from a copy of a head pointer of the accelerator'"'"'s descriptor array maintained on the host computer, the head pointer configured to point to next available element of the accelerator'"'"'s descriptor array;

incrementing, by the host computer, the copy of the head pointer of the accelerator'"'"'s descriptor array maintained on the host computer; and

updating, by the host computer, a copy of the head pointer of the accelerator'"'"'s descriptor array maintained on the accelerator with the incremented copy.

2. The method of claim 1 further comprising:

determining, by the host computer, whether the accelerator'"'"'s shared memory is full;

if the accelerator'"'"'s shared memory is full;

identifying one or more processed descriptors, by the host computer in dependence upon a copy of a tail pointer of the accelerator'"'"'s descriptor array maintained on the host computer and the host computer'"'"'s copy of the head pointer of the accelerator'"'"'s descriptor array; and

freeing, by the host computer in the shadow memory area of the host computer, regions of memory corresponding to the identified processed descriptors; and

allocating a memory region, writing packet data, inserting a descriptor, incrementing the host computer'"'"'s copy of the head pointer, and updating the accelerator'"'"'s head pointer only if the accelerator'"'"'s shared memory is not full.

3. The method of claim 2 wherein determining whether the accelerator'"'"'s shared memory is full further comprises:

determining, in dependence upon the host computer'"'"'s copy of the tail pointer for the accelerator'"'"'s descriptor array and the host computer'"'"'s copy of the head pointer for the accelerator'"'"'s descriptor array, whether at least one descriptor in the accelerator'"'"'s descriptor array has been processed by subtracting, with modulo arithmetic, the host computer'"'"'s copy of the tail pointer for the accelerator'"'"'s descriptor array from the host computer'"'"'s copy of the head pointer for the accelerator'"'"'s descriptor array.

4. The method of claim 2 wherein determining whether the accelerator'"'"'s shared memory is full further comprises determining whether the host computer'"'"'s shadow memory area is full.

5. The method of claim 1 further comprising reading, by the accelerator, the packet data from the accelerator'"'"'s shared memory, including:

identifying a non-processed descriptor in the accelerator'"'"'s descriptor array;

copying, by the accelerator in dependence upon the non-processed descriptor, packet data from the accelerator'"'"'s shared memory to the accelerator'"'"'s user-level memory;

incrementing a copy of the tail pointer of the accelerator'"'"'s descriptor array maintained on the accelerator; and

updating a copy of the tail pointer of the accelerator'"'"'s descriptor array maintained on the host computer with the incremented copy of the tail pointer maintained on the accelerator.

6. The method of claim 5 wherein identifying a non-processed descriptor further comprises identifying a non-processed descriptor further comprises subtracting, with modulo arithmetic, the accelerator'"'"'s copy of the tail pointer for the accelerator'"'"'s descriptor array from the accelerator'"'"'s copy of the head pointer for the accelerator'"'"'s descriptor array.

7. The method of claim 1 further comprising:

allocating, in a shadow memory area of the accelerator, a memory region for a packet to be written to the shared memory of the host computer;

writing packet data by the accelerator to the host computer'"'"'s shared memory in a memory region corresponding to the allocated memory region in the accelerator'"'"'s shadow memory area;

inserting, by the accelerator in a next available element of a descriptor array of the host computer, a descriptor identifying the written packet data including identifying the next available element of the host computer'"'"'s descriptor array from a copy of a head pointer of the host computer'"'"'s descriptor array maintained on the accelerator, the head pointer configured to point to next available element of the host computer'"'"'s descriptor array;

incrementing, by the accelerator, the copy of the head pointer of the host computer'"'"'s descriptor array maintained on the accelerator; and

updating, by the accelerator, a copy of the head pointer of the host computer'"'"'s descriptor array maintained on the host computer with the incremented copy.

8. The method of claim 7 further comprising reading, by the host computer, the packet data from the host computer'"'"'s shared memory, including:

identifying a non-processed descriptor in the host computer'"'"'s descriptor array;

copying, in dependence upon the non-processed descriptor, packet data from the host computer'"'"'s shared memory to the host computer'"'"'s user-level memory;

incrementing a copy of the tail pointer of the host computer'"'"'s descriptor array maintained on the host computer; and

updating a copy of the tail pointer of the host computer'"'"'s descriptor array maintained on the accelerator with the incremented copy of the tail pointer maintained on the host computer.

9. A hybrid computing environment for reducing remote reads of memory in a hybrid computing environment, the hybrid computing environment comprising a host computer having a host computer architecture, a plurality of accelerators having an accelerator architecture, the accelerator architecture optimized, with respect to the host computer architecture, for speed of execution of a particular class of computing functions, the host computer and the accelerators adapted to one another for data communications by a system level message passing module, the host computer having local memory shared remotely with the accelerators and having a shadow memory area, each accelerator having local memory shared remotely with the host computer, each accelerator comprising a descriptor array, the descriptor array comprising a plurality of elements, each element of the descriptor array capable of storing a descriptor identifying packet data to be read from the accelerator'"'"'s shared memory, the hybrid computing environment comprising computer program instructions capable of:

allocating, by the host computer in the shadow memory area of the host computer, a memory region for a packet to be written to the shared memory of an accelerator;

writing packet data by the host computer to the accelerator'"'"'s shared memory in a memory region corresponding to the allocated memory region in the host computer'"'"'s shadow memory area;

inserting, by the host computer in a next available element of the accelerator'"'"'s descriptor array, a descriptor identifying the written packet data including identifying the next available element of the accelerator'"'"'s descriptor array from a copy of a head pointer of the accelerator'"'"'s descriptor array maintained on the host computer, the head pointer configured to point to next available element of the accelerator'"'"'s descriptor array;

incrementing, by the host computer, the copy of the head pointer of the accelerator'"'"'s descriptor array maintained on the host computer; and

updating, by the host computer, a copy of the head pointer of the accelerator'"'"'s descriptor array maintained on the accelerator with the incremented copy.

10. The hybrid computing environment of claim 9 further comprising computer program instructions capable of:

determining, by the host computer, whether the accelerator'"'"'s shared memory is full;

if the accelerator'"'"'s shared memory is full;

identifying one or more processed descriptors, by the host computer in dependence upon a copy of a tail pointer of the accelerator'"'"'s descriptor array maintained on the host computer and the host computer'"'"'s copy of the head pointer of the accelerator'"'"'s descriptor array; and

freeing, by the host computer in the shadow memory area of the host computer, regions of memory corresponding to the identified processed descriptors; and

allocating a memory region, writing packet data, inserting a descriptor, incrementing the host computer'"'"'s copy of the head pointer, and updating the accelerator'"'"'s head pointer only if the accelerator'"'"'s shared memory is not full.

11. The hybrid computing environment of claim 10 wherein determining whether the accelerator'"'"'s shared memory is full further comprises:

determining, in dependence upon the host computer'"'"'s copy of the tail pointer for the accelerator'"'"'s descriptor array and the host computer'"'"'s copy of the head pointer for the accelerator'"'"'s descriptor array, whether at least one descriptor in the accelerator'"'"'s descriptor array has been processed by subtracting, with modulo arithmetic, the host computer'"'"'s copy of the tail pointer for the accelerator'"'"'s descriptor array from the host computer'"'"'s copy of the head pointer for the accelerator'"'"'s descriptor array.

12. The hybrid computing environment of claim 10 wherein determining whether the accelerator'"'"'s shared memory is full further comprises determining whether the host computer'"'"'s shadow memory area is full.

13. The hybrid computing environment of claim 9 further comprising computer program instructions capable of reading, by the accelerator, the packet data from the accelerator'"'"'s shared memory, including:

identifying a non-processed descriptor in the accelerator'"'"'s descriptor array;

copying, by the accelerator in dependence upon the non-processed descriptor, packet data from the accelerator'"'"'s shared memory to the accelerator'"'"'s user-level memory;

incrementing a copy of the tail pointer of the accelerator'"'"'s descriptor array maintained on the accelerator; and

updating a copy of the tail pointer of the accelerator'"'"'s descriptor array maintained on the host computer with the incremented copy of the tail pointer maintained on the accelerator.

14. The hybrid computing environment of claim 13 wherein identifying a non-processed descriptor further comprises, identifying a non-processed descriptor further comprises subtracting, with modulo arithmetic, the accelerator'"'"'s copy of the tail pointer for the accelerator'"'"'s descriptor array from the accelerator'"'"'s copy of the head pointer for the accelerator'"'"'s descriptor array.

15. The hybrid computing environment of claim 9 further comprising computer program instructions capable of:

allocating, in a shadow memory area of the accelerator, a memory region for a packet to be written to the shared memory of the host computer;

writing packet data by the accelerator to the host computer'"'"'s shared memory in a memory region corresponding to the allocated memory region in the accelerator'"'"'s shadow memory area;

inserting, by the accelerator in a next available element of a descriptor array of the host computer, a descriptor identifying the written packet data including identifying the next available element of the host computer'"'"'s descriptor array from a copy of a head pointer of the host computer'"'"'s descriptor array maintained on the accelerator, the head pointer configured to point to next available element of the host computer'"'"'s descriptor array;

incrementing, by the accelerator, the copy of the head pointer of the host computer'"'"'s descriptor array maintained on the accelerator; and

updating, by the accelerator, a copy of the head pointer of the host computer'"'"'s descriptor array maintained on the host computer with the incremented copy.

16. The hybrid computing environment of claim 15 further comprising computer program instructions capable of reading, by the host computer, the packet data from the host computer'"'"'s shared memory, including:

identifying a non-processed descriptor in the host computer'"'"'s descriptor array;

copying, in dependence upon the non-processed descriptor, packet data from the host computer'"'"'s shared memory to the host computer'"'"'s user-level memory;

incrementing a copy of the tail pointer of the host computer'"'"'s descriptor array maintained on the host computer; and

updating a copy of the tail pointer of the host computer'"'"'s descriptor array maintained on the accelerator with the incremented copy of the tail pointer maintained on the host computer.

17. A computer program product for reducing remote reads of memory in a hybrid computing environment, the hybrid computing environment comprising a host computer having a host computer architecture, a plurality of accelerators having an accelerator architecture, the accelerator architecture optimized, with respect to the host computer architecture, for speed of execution of a particular class of computing functions, the host computer and the accelerators adapted to one another for data communications by a system level message passing module, the host computer having local memory shared remotely with the accelerators and having a shadow memory area, each accelerator having local memory shared remotely with the host computer, each accelerator comprising a descriptor array, the descriptor array comprising a plurality of elements, each element of the descriptor array capable of storing a descriptor identifying packet data to be read from the accelerator'"'"'s shared memory, the computer program product disposed in a non-transitory computer readable storage medium, the computer program product comprising computer program instructions capable of:

allocating, by the host computer in the shadow memory area of the host computer, a memory region for a packet to be written to the shared memory of an accelerator;

writing packet data by the host computer to the accelerator'"'"'s shared memory in a memory region corresponding to the allocated memory region in the host computer'"'"'s shadow memory area;

inserting, by the host computer in a next available element of the accelerator'"'"'s descriptor array, a descriptor identifying the written packet data including identifying the next available element of the accelerator'"'"'s descriptor array from a copy of a head pointer of the accelerator'"'"'s descriptor array maintained on the host computer, the head pointer configured to point to next available element of the accelerator'"'"'s descriptor array;

incrementing, by the host computer, the copy of the head pointer of the accelerator'"'"'s descriptor array maintained on the host computer; and

updating, by the host computer, a copy of the head pointer of the accelerator'"'"'s descriptor array maintained on the accelerator with the incremented copy.

18. The computer program product of claim 17 further comprising computer program instructions capable of:

determining, by the host computer, whether the accelerator'"'"'s shared memory is full;

if the accelerator'"'"'s shared memory is full;

identifying one or more processed descriptors, by the host computer in dependence upon a copy of a tail pointer of the accelerator'"'"'s descriptor array maintained on the host computer and the host computer'"'"'s copy of the head pointer of the accelerator'"'"'s descriptor array; and

freeing, by the host computer in the shadow memory area of the host computer, regions of memory corresponding to the identified processed descriptors; and

allocating a memory region, writing packet data, inserting a descriptor, incrementing the host computer'"'"'s copy of the head pointer, and updating the accelerator'"'"'s head pointer only if the accelerator'"'"'s shared memory is not full.

19. The computer program product of claim 17 further comprising computer program instructions capable of reading, by the accelerator,the packet data from the accelerator'"'"'s shared memory, including:

identifying a non-processed descriptor in the accelerator'"'"'s descriptor array;

copying, by the accelerator in dependence upon the non-processed descriptor, packet data from the accelerator'"'"'s shared memory to the accelerator'"'"'s user-level memory;

incrementing a copy of the tail pointer of the accelerator'"'"'s descriptor array maintained on the accelerator; and

updating a copy of the tail pointer of the accelerator'"'"'s descriptor array maintained on the host computer with the incremented copy of the tail pointer maintained on the accelerator.

20. The computer program product of claim 19 wherein identifying a non-processed descriptor further comprises identifying a non-processed descriptor further comprises subtracting, with modulo arithmetic, the accelerator'"'"'s copy of the tail pointer for the accelerator'"'"'s descriptor array from the accelerator'"'"'s copy of the head pointer for the accelerator'"'"'s descriptor array.

21. The computer program product of claim 17 further comprising computer program instructions capable of:

allocating, in a shadow memory area of the accelerator, a memory region for a packet to be written to the shared memory of the host computer;

writing packet data by the accelerator to the host computer'"'"'s shared memory in a memory region corresponding to the allocated memory region in the accelerator'"'"'s shadow memory area;

inserting, by the accelerator in a next available element of a descriptor array of the host computer, a descriptor identifying the written packet data including identifying the next available element of the host computer'"'"'s descriptor array from a copy of a head pointer of the host computer'"'"'s descriptor array maintained on the accelerator, the head pointer configured to point to next available element of the host computer'"'"'s descriptor array;

incrementing, by the accelerator, the copy of the head pointer of the host computer'"'"'s descriptor array maintained on the accelerator; and

updating, by the accelerator, a copy of the head pointer of the host computer'"'"'s descriptor array maintained on the host computer with the incremented copy.

22. The computer program product of claim 21 further comprising computer program instructions capable of reading, by the host computer, the packet data from the host computer'"'"'s shared memory, including:

identifying a non-processed descriptor in the host computer'"'"'s descriptor array;

copying, in dependence upon the non-processed descriptor, packet data from the host computer'"'"'s shared memory to the host computer'"'"'s user-level memory;

incrementing a copy of the tail pointer of the host computer'"'"'s descriptor array maintained on the host computer; and

updating a copy of the tail pointer of the host computer'"'"'s descriptor array maintained on the accelerator with the incremented copy of the tail pointer maintained on the host computer.