Managing power of thread pipelines according to clock frequency and voltage specified in thread registers

• US 9,015,504 B2
• Filed: 01/06/2011
• Issued: 04/21/2015
• Est. Priority Date: 08/30/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Tran, Thang
• Primary Examiner(s): KIM, KENNETH S
• Application Number:
  US12/986,127
• Publication Number:
  US 20110099393A1
• Time in Patent Office: 1,566 Days
• Field of Search: None
• US Class Current: 713/320
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/324 using program counter relative addressing
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A multi-threaded microprocessor for processing instructions in threads, including, in one embodiment, (1) at least one processor pipeline for the instructions; (2) a storage for a thread power management configuration; and (3) a power control circuit coupled to said at least one processor pipeline and responsive to said storage for thread power management configuration to control power used by different parts of the at least one processor pipeline depending on the threads, wherein said power control circuit is operable to establish different power voltages in different parts of the at least one processor pipeline depending on the threads.

Claims

1. A microprocessor comprising:

(A) clock signal circuitry having clock outputs of different frequency rates;

(B) power supply circuitry having voltage outputs of different voltages;

(C) thread pipelines having clock signal inputs and voltage inputs; and

(E) thread register control circuitry having inputs coupled to the clock outputs and the voltage outputs, and having outputs coupled to the clock signal inputs and voltage inputs of the thread pipelines, the thread register control circuitry including thread power management circuitry having registers for thread identification, pipe clock rate, and pipe voltage.

2. The microprocessor of claim 1 in which a register for thread identification corresponds to one register for pipe clock rate and one register for pipe voltage.

3. The microprocessor of claim 1 in which there are multiple registers for thread identification.

4. The microprocessor of claim 1 in which there are multiple registers for thread identification, and in which a register for thread identification corresponds to one register for pipe clock rate and one register for pipe voltage.

5. The microprocessor of claim 1 in which a thread pipeline includes a decode pipe having a clock input and a voltage input, and an execute pipe having a clock input and a voltage input separate from those of the decode pipe.