Non main CPU/OS based operational environment

• US 9,015,511 B2
• Filed: 08/27/2013
• Issued: 04/21/2015
• Est. Priority Date: 02/14/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kardach, James P., Belmont, Brian V., Kumar, Muthu K., Jackson, Riley W., Danneels, Gunner D., Forand, Richard A., Gupta, Vivek, Huckins, Jeffrey L., Fleming, Kristoffer D., Gadamsetty, Uma M.
• Primary Examiner(s): SHIN, CHRISTOPHER B
• Application Number:
  US14/010,852
• Publication Number:
  US 20130346664A1
• Time in Patent Office: 602 Days
• Field of Search: 713/323, 710/15
• US Class Current: 713/323
• CPC Class Codes: G06F 1/266 Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: G10L 19/04 using predictive techniques
• CPC Class Codes: H04R 1/1091 Details not provided for in groups H04R1/1008 - H04R1/1083
• CPC Class Codes: H04R 2201/109 Arrangements to adapt hands free headphones for use on both ears
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.

Claims

1. At least one non-transitory machine-readable medium comprising one or more instructions which, if executed by a computing system, causes the computing system to:

save an operating environment of the computing system;

set a power consumption state for the computing system via logic including a bit that is to be set when the computing system is to transition to a relatively lower power operation state, wherein the bit is to indicate that the power consumption state specific to the relatively lower power operation state is to be engaged to disable at least a main processor to place the main processor in an inactive state when the computing system is to enter the relatively lower power operation state and wherein system memory of the computing system is to be inactive in the relatively lower power operation state; and

execute a function from the relatively lower power operation state, wherein at least one component of the computing system is to remain active to implement the relatively lower power operation state.

2. The medium of claim 1, wherein the operating environment is to include one or more of a state of a routine and data of a routine.

3. The medium of claim 1, wherein one or more of another processor and a main system bus of the computing system is to remain active to implement the relatively lower power operation state.

4. The medium of claim 1, wherein the instructions, if executed, further cause the computing system to:

transition out of the relatively lower power operation state; and

activate the main processor.

5. The medium of claim 1, wherein the instructions, if executed, further cause the computing system to:

record that the main processor is to be placed in the inactive state due to the computing system entering the relatively lower power consumption state by a write to the bit; and

recognize that the computing system is to transition from the relatively lower power operation state and not from a non operational sleep state by a read from the bit.

6. The medium of claim 1, wherein the instructions, if executed, further cause the computing system to selectively activate a component of the computing system specific to a usage of the computing system.

7. The medium of claim 1, wherein the instructions, if executed, further cause the computing system to transition out of the relatively lower power operation state in response to a need to use a function that is not operable within the relatively lower power operation state.

8. The medium of claim 1, wherein the instructions, if executed, further cause the computing system to enter a relatively higher power operation state, wherein the relatively higher power operation state is to include at least one inactive component.

9. The medium of claim 1, wherein the instructions, if executed, further cause the computing system to restore the saved operating environment.

10. The medium of claim 1, wherein the instructions, if executed, further cause the computing system to remove power to the main processor to disable the main processor.

11. The medium of claim 1, wherein the instructions, if executed, further cause the computing system to logically disable one or more of the main processor and a component of the computing system.

12. A method comprising:

saving an operating environment of a computing system;

setting a power consumption state for the computing system via logic including a bit that is set when the computing system transitions to a relatively lower power operation state, wherein the bit indicates that the power consumption state specific to the relatively lower power operation state is engaged to disable at least a main processor to place the main processor in an inactive state when the computing system enters the relatively lower power operation state and wherein system memory of the computing system is to be inactive in the relatively lower power operation state; and

executing a function from the relatively lower power operation state, wherein at least one component of the computing system remains active to implement the relatively lower power operation state.

13. The method of claim 12, further including:

transitioning out of the relatively lower power operation state; and

activating the main processor.

14. The method of claim 12, further including:

recording that the main processor is placed in the inactive state due to the computing system entering the relatively lower power consumption state by writing to the bit; and

recognizing that the computing system transitions from the relatively lower power operation state and not from a non operational sleep state by reading from the bit.

15. The method of claim 12, further including:

selectively activating a component of the computing system specific to a usage of the computing system; and

transitioning out of the relatively lower power operation state in response to a need to use a function that is not operable within the relatively lower power operation state.

16. The method of claim 12, further including:

entering a relatively higher power operation state, wherein the relatively higher power operation state includes at least one inactive component; and

restoring the saved operating environment.

17. The method of claim 12, further including:

removing power to the main processor to disable the main processor; and

logically disabling a component of the computing system.

18. An apparatus comprising:

logic including a bit that is to be set when the apparatus is to transition to a relatively lower power operation state, wherein the bit is to indicate that a power consumption state specific to the relatively lower power operation state is to be engaged to disable at least a main processor to place the main processor in an inactive state when the apparatus is to enter the relatively lower power operation state and wherein system memory of the computing system is to be inactive in the relatively lower power operation state; and

at least one component that is to remain active to implement the relatively lower power operation state.

19. The apparatus of claim 18, wherein:

the bit is to be written to for a record that the main processor is to be placed in the inactive state due to the computing system entering the relatively lower power consumption state; and

the bit is to be read to recognize that the apparatus is to transition from the relatively lower power operation state and not from a non operational sleep state.