Bit error rate based wear leveling for solid state drive memory

• US 9,015,537 B2
• Filed: 12/10/2013
• Issued: 04/21/2015
• Est. Priority Date: 01/20/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Griffin, Thomas J., Vanstee, Dustin J.
• Primary Examiner(s): Tabone, Jr., John J
• Application Number:
  US14/101,655
• Publication Number:
  US 20140101499A1
• Time in Patent Office: 497 Days
• Field of Search: 714/704, 714/718, 714/736, 714/746, 714/754, 714/759, 714/760, 714/774, 714/799
• US Class Current: 714/704
• CPC Class Codes: G01R 31/3171 BER [Bit Error Rate] test
• CPC Class Codes: G06F 11/008 Reliability or availability analysis
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/16 Error detection or correction of the data by redundancy in hardware
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3409 Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: H04L 1/203 Details of error rate determination, e.g. BER, FER or WER

Abstract

According to exemplary embodiments, a system, is provided for bit error rate (BER)-based wear leveling in a solid state drive (SSD). A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.

Claims

1. A system for bit error rate (BER) based wear leveling in a solid state drive (SSD), the system comprising:

a program/erase (PE) cycle adjustment module and a plurality of blocks comprising solid state memory, the system configured to perform a method comprising;

determining a block-level BER value for a block of the plurality of blocks;

incrementing or decrementing an adjusted PE cycle count for the block based on the block-level BER value by the PE cycle adjustment module; and

performing wear leveling in the SSD based on the adjusted PE cycle count by distributing PE cycling among a plurality of blocks in the SSD based on a respective adjusted PE cycle count of each of the plurality of blocks in the SSD.

2. The system of claim 1, wherein determining the block-level BER statistics for the block comprises collecting error correcting code (ECC) data from one or more read events of one or more pages in the block, and wherein determining the adjusted PE cycle count for the block based on the block-level BER value is performed in response to an erase event in the block.

3. The system of claim 1, wherein determining the adjusted PE cycle count for the block based on the block-level BER value comprises comparing the block-level BER value and the adjusted PE cycle count of the block to a lookup table, wherein the lookup table comprises a plurality of ranges of expected PE cycle count values, each of the plurality of ranges of expected PE cycle count values being mapped to a respective BER value.

4. The system of claim 3, wherein the lookup table is modified based on observed actual PE cycle count values received from the plurality of blocks by the PE cycle adjustment module.

5. The system of claim 4, wherein the adjusted PE cycle count of the block is incremented to be equal to a midpoint of the range of expected PE cycle count values given by the lookup table for the BER value of the block based on the incremented adjusted PE cycle count being lower than the minimum threshold of the range of expected PE cycle count values plus the margin.

6. The system of claim 3, wherein the adjusted PE cycle count of the block is incremented based on the adjusted PE cycle count being lower than a minimum threshold of the range of expected PE cycle count values given by the lookup table for the BER value of the block.

7. The system of claim 6, wherein the adjusted PE cycle count of the block is decremented to be equal to the maximum threshold of the range of expected PC cycle count values given by the lookup table for the BER value of the block based on the adjusted PE cycle count being higher than a maximum threshold of the range of expected PE cycle count values given by the lookup table for the BER value of the block.

8. The system of claim 3, wherein the adjusted PE cycle count of the block is incremented based on the incremented adjusted PE cycle count being lower than the minimum threshold of the range of expected PE cycle count values plus a margin.

9. The system of claim 8, wherein the adjusted PE cycle count of the block is decremented to be equal to a midpoint of the range of expected PC cycle count values given by the lookup table for the BER value of the block based on the decremented adjusted PE cycle count being higher than the maximum threshold of the range of expected PE cycle count values minus the margin.

10. The system of claim 3, wherein the adjusted PE cycle count of the block is decremented based on the adjusted PE cycle count being higher than a maximum threshold of the range of expected PE cycle count values given by the lookup table for the BER value of the block.

11. The system of claim 3, wherein the adjusted PE cycle count of the block is decremented based on the decremented adjusted PE cycle count being higher than the maximum threshold of the range of expected PE cycle count values minus a margin.

12. The system of claim 3, wherein the adjusted PE cycle count of the block is incremented to be equal to the minimum threshold of the range of expected PE cycle count values given by the lookup table for the BER value of the block based on the adjusted PE cycle count being lower than the minimum threshold of the range of expected PE cycle count values given by the lookup table for the BER value of the block.

13. The system of claim 1, further comprising maintaining both the adjusted PE cycle count for the block and an actual PE cycle count for the block by a PE cycle count module of the block.

14. The system of claim 13, further comprising:

providing the BER value for the block and the actual PE cycle count for the block from the PE cycle count module to a PE adjustment module; and

modifying a lookup table, wherein the lookup table comprises a plurality of ranges of expected PE cycle count values, each of the plurality of ranges of expected PE cycle count values being mapped to a respective BER value, based on the received BER value for the block and the received actual PE cycle count for the block by the PE adjustment module during operation of the SSD.

15. The system of claim 13, further comprising:

based on BER based wear leveling being enabled for the SSD, providing the adjusted PE cycle count to a wear leveling module that performs the wear leveling, and performing wear leveling by the wear leveling module based on the adjusted PE cycle count; and

based on BER based wear leveling not being enabled for the SSD, providing the actual PE cycle count to the wear leveling module that performs the wear leveling, and performing wear leveling by the wear leveling module based on the actual PE cycle count.