Wafer structure and power device using the same

• US 9,018,062 B2
• Filed: 02/03/2014
• Issued: 04/28/2015
• Est. Priority Date: 03/05/2013
• Status: Active Grant

• Current Assignee: Hangzhou Silicon-Magic Semiconductor Technology Company Limited
• Original Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd. (Silergy Corporation)
• Inventors: Liao, Zhongping
• Primary Examiner(s): Lee, Hsien Ming
• Application Number:
  US14/170,731
• Publication Number:
  US 20140252553A1
• Time in Patent Office: 449 Days
• Field of Search: 257/262, 257/263, 257/328, 257/329, 257/335, 438268-272, 438/316, 438/336
• US Class Current: 438/268
• CPC Class Codes: H01L 21/18 the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials H01L21/041 - H01L21/0425, H01L21/045 - H01L21/048 take precedence
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/861 Diodes

Abstract

In one embodiment, a method of making a super-junction MOS transistor in a wafer can include: (i) forming a first doping layer having a high doping concentration; (ii) forming a second doping layer on the first doping layer, wherein a doping concentration of the second doping layer is less than a doping concentration of the first doping layer; (iii) forming a third doping layer on the second doping layer, wherein the third doping layer comprises an intrinsic layer; (iv) etching through the third doping layer and partially through the second doping layer to form trenches; and (v) filling the trenches to form pillar structures.

Claims

1. A wafer structure for a power device, the wafer structure comprising:

a) a first doping layer having a high doping concentration;

b) a second doping layer on said first doping layer, wherein a doping concentration of said second doping layer is less than said high doping concentration;

c) a third doping layer on said second doping layer, wherein a doping concentration of said third doping layer is less than said doping concentration of said second doping layer; and

d) pillar structures extending through said third doping layer and partially through said second doping layer, wherein each of said pillar structures comprises a bowl structure extending an entire thickness of said third doping layer.

2. The wafer structure of claim 1, wherein said third doping layer comprises an intrinsic layer.

3. The wafer structure of claim 1, wherein said doping concentration of said second doping layer is uniformly distributed.

4. The wafer structure of claim 1, wherein said doping concentration of said second doping layer is gradiently distributed.

5. The wafer structure of claim 1, wherein a type of impurity of said second doping layer is the same as a type of impurity of said first doping layer.

6. The wafer structure of claim 1, wherein a type of impurity of said second doping layer is different than a type of impurity of said first doping layer.

7. The wafer structure of claim 1, wherein said second and third doping layers are formed by epitaxial growth on said first doping layer.

8. A switching voltage regulator, comprising:

a) said wafer structure of claim 1; and

b) said power device formed in said wafer structure.

9. The switching voltage regulator of claim 8, wherein said power device comprises a metal oxide semiconductor field-effect transistor (MOSFET).

10. The switching voltage regulator of claim 9, wherein said MOSFET comprises a longitude super-junction metal oxide field-effect transistor or a vertical double diffused metal oxide semiconductor field-effect transistor.

11. The switching voltage regulator of claim 10, wherein said longitude super-junction metal oxide field-effect transistor is manufactured by a trench fill process.

12. The switching voltage regulator of claim 9, wherein said MOSFET comprises a vertical double diffused metal oxide semiconductor field-effect transistor.

13. The switching voltage regulator of claim 8, wherein said power device comprises an insulated gate bipolar transistor (IGBT).

14. The switching voltage regulator of claim 8, wherein said power device comprises a diode.

15. A method of making a super-junction MOS transistor in a wafer, the method comprising:

a) forming a first doping layer having a high doping concentration;

b) forming a second doping layer on said first doping layer, wherein a doping concentration of said second doping layer is less than a doping concentration of said first doping layer;

c) forming a third doping layer on said second doping layer, wherein said third doping layer comprises an intrinsic layer;

d) etching through said third doping layer and partially through said second doping layer to form trenches; and

e) filling said trenches to form pillar structures, wherein each of said pillar structures comprises a bowl structure extending an entire thickness of said third doping layer.

16. The method of claim 15, wherein said forming said first doping layer comprises heavily doping a silicon substrate with n-type impurities.

17. The method of claim 15, wherein said forming said second doping layer comprises lightly doping said second doping layer with n-type impurities.

18. The method of claim 15, wherein said filling said trenches comprises using silicon material with p-type impurities therein.

19. The method of claim 15, wherein said bowl structure in said third doping layer is configured to extend a terminal surface for a super-junction MOS transistor.

20. The method of claim 15, further comprising:

a) forming a field oxide on a surface of said pillar structures and said third doping layer; and

b) depositing a metal layer at least partially on said field oxide.