ESD protection device and method

• US 9,018,072 B2
• Filed: 01/30/2014
• Issued: 04/28/2015
• Est. Priority Date: 01/20/2010
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Gendron, Amaury, Gill, Chai Ean, Hong, Changsoo
• Primary Examiner(s): Pert, Evan
• Assistant Examiner(s): ASSOUMAN, HERVE-LOUIS Y
• Application Number:
  US14/168,813
• Publication Number:
  US 20140147983A1
• Time in Patent Office: 453 Days
• Field of Search: None
• US Class Current: 438/335
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/66234 Bipolar junction transistors [BJT]
• CPC Class Codes: H01L 29/6625 Lateral transistors H01L29/66242 and H01L29/66265 take precedence
• CPC Class Codes: H01L 29/735 Lateral transistors

Abstract

An electrostatic discharge (ESD) protection clamp (21, 21′, 70, 700) for protecting associated devices or circuits (24), comprises a bipolar transistors (21, 21′, 70, 700) in which doping of facing base (75) and collector (86) regions is arranged so that avalanche breakdown occurs preferentially within a portion (84, 85) of the base region (74, 75) of the device (70, 700) away from the overlying dielectric-semiconductor interface (791). Maximum variations (ΔVt1)_MAX of ESD triggering voltage Vt1 as a function of base-collector spacing dimensions D due, for example, to different azimuthal orientations of transistors (21, 21′, 70, 700) on a semiconductor die or wafer is much reduced. Triggering voltage consistency and manufacturing yield are improved.

Claims

1. A method for forming a bipolar transistor electrostatic discharge (ESD) clamp, comprising:

providing a semiconductor substrate having a first region of a first conductivity type or a second conductivity type and first and second dopant density, respectively, extending to a first surface;

forming a first WELL region of a third conductivity type and third doping density extending from the first surface into the first region and having a first lateral boundary;

forming a second WELL region of a fourth conductivity type opposite the third conductivity type and having a fourth doping density extending into the first WELL region and having a second lateral boundary separated from the first lateral boundary by a minimum distance D across an intermediate portion of the first region having a fifth dopant density; and

forming a dielectric-semiconductor interface overlying at least the intermediate portion;

wherein either;

(i) the minimum distance D is located beneath the dielectric-semiconductor interface by a distance Y>

0, or (ii) the third and fourth doping densities exceed the fifth doping density at a distance Y>

0 below the dielectric-semiconductor interface by at least a factor of 5, or (iii) both (i) and (ii).

2. The method of claim 1, wherein Y≧

0.1 micrometers.

3. The method of claim 2, wherein Y≧

0.2 micrometers.

4. The method of claim 1, wherein the third and fourth doping densities exceed the fifth doping density at a distance Y below the dielectric-semiconductor interface by at least a factor of 10.

5. The method of claim 1, wherein:

the step of providing a semiconductor substrate comprises providing a semiconductor substrate that has first and second laterally arranged regions of a first or second conductivity type extending to a first surface, and wherein;

the step of forming a first WELL region comprises forming a first WELL region of a third conductivity type and third doping density extending from the first surface between the first and second laterally arranged regions, so that the first WELL region and has a first lateral boundary in the first region and a second lateral boundary in the second region; and

wherein

the step of forming a second WELL region comprises forming first and second spaced-apart second WELL regions of a fourth conductivity type opposite the third conductivity type and having a fourth doping density and extending, respectively, into the first and second regions, wherein the first of the second WELL regions has a third lateral boundary spaced apart from the first lateral boundary by a distance D across a first intermediate portion of the first region having the fifth dopant density, and the second of the second WELL regions has a fourth lateral boundary spaced apart from the second lateral boundary by a distance DR across a second intermediate portion of the first region having the fifth doping density, and wherein;

the step of forming a dielectric-semiconductor interface, comprises forming a dielectric-semiconductor interface overlying the first intermediate portion and forming a dielectric-semiconductor interface overlying the second intermediate portion, and wherein;

the distances D and DR are located beneath the dielectric-semiconductor interfaces, respectively, by depths Y_D>

0 and Y_DR>

0, respectively.

6. The method of claim 5, wherein D and DR are substantially equal.

7. The method of claim 5, further comprising providing first and second contact regions of the third conductivity type and third and fourth contact regions of the fourth conductivity type in the first and second spaced apart second WELL regions, wherein the first and third contact regions are coupled together and to a first terminal of the bipolar transistor electrostatic discharge (ESD) clamp and the second and fourth contact regions are coupled together and to a second terminal of the bipolar transistor electrostatic discharge (ESD) clamp.

8. A method for forming a bipolar transistor electrostatic discharge (ESD) clamp coupled to first and second external terminals between which a core circuit is coupled, the method comprising:

forming an emitter region of a first doping density electrically coupled to the first terminal;

forming a collector region of a second doping density electrically coupled to the second terminal;

forming a base region of a third doping density located between the emitter region and the collector region; and

forming a further region of a fourth doping density located between the base region and the collector region, at least the further region extending to an overlying dielectric-semiconductor interface;

wherein the base region has a first dopant boundary with the further region and the collector region has a second dopant boundary with the further region; and

wherein at least one of the first and second dopant boundaries has a maximum dopant density at a distance Y>

0 beneath the dielectric-semiconductor interface.

9. The method of claim 8, wherein Y>

0.1 micrometer.

10. The method of claim 8, further comprising forming the first and second dopant boundaries to have maximum dopant concentrations at distances Y1 and Y2, respectively, beneath the dielectric-semiconductor interface, wherein Y1>

0 and Y2>

0.

11. The method of claim 8, wherein the base region and the collector region are more doped more heavily than is the further region.

12. The method of claim 8, wherein the peak dopant concentration of the base region and the peak dopant concentration of the collector region exceed the average dopant concentration of the further region by a factor of at least 10.

13. The method of claim 8, wherein the emitter region and a base contact region are substantially shorted together.

14. The method of claim 8, wherein the first and second dopant boundaries are separated by a minimum distance D through the further region, and wherein the minimum distance D occurs at a depth Y>

0 beneath the dielectric-semiconductor interface.

15. The method of claim 14, wherein the bipolar transistor ESD clamp is adapted to have an avalanche trigger voltage Vt1 substantially determined by D.

16. A method for producing a bipolar transistor electrostatic discharge (ESD) clamp coupled to first and second terminals, the method comprising:

forming in a substrate an emitter coupled to the first terminal;

forming in the substrate a collector coupled to the second terminal;

forming in the substrate a base between the emitter and the collector;

forming a dielectric-semiconductor interface at or near a first surface of the substrate; and

producing the bipolar transistor ESD clamp to further include an intermediate semiconductor portion in the substrate, which is coupled between the base and the collector, which is more lightly doped than the base and the collector, and which extends to the dielectric-semiconductor interface;

wherein the intermediate semiconductor portion has a first interface with the base and second interface with the collector extending away from the dielectric-semiconductor interface; and

wherein the first and second interfaces have a minimum separation D located a distance Y>

0 below the dielectric-semiconductor interface.

17. The method of claim 16, wherein Y>

0.1 micrometers.

18. The method of claim 16, further comprising forming a buried layer region underlying the base and Ohmically coupled to the collector.