Non-planar semiconductor device having active region with multi-dielectric gate stack

• US 9,018,680 B2
• Filed: 07/25/2014
• Issued: 04/28/2015
• Est. Priority Date: 09/27/2012
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Dewey, Gilbert, Radosavljevic, Marko, Pillarisetty, Ravi, Chu-Kung, Benjamin, Mukherjee, Niloy
• Primary Examiner(s): YUSHIN, NIKOLAY K
• Application Number:
  US14/340,981
• Publication Number:
  US 20140332852A1
• Time in Patent Office: 277 Days
• Field of Search: 257/192, 257/288, 257/330
• US Class Current: 257/192
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 99/00 Subject matter not provided for in other groups of this subclass
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/201 including two or more compounds , e.g. alloys H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate comprising a first semiconductor material;

a second layer above the semiconductor substrate, the second layer comprising a second material different from the first semiconductor material;

a nanowire above the second layer, the nanowire comprising a third material different than the second material, the nanowire having a channel region;

a source region to a first side of the channel region and having a top, the source region top being above a top of the nanowire;

a drain region to a second side of the channel region, the second side of the channel region being opposite the first side, the drain region having a top, the drain region top being above the top of the nanowire;

a first gate dielectric layer around the channel region of the nanowire;

a second gate dielectric layer around the channel region of the nanowire, the second gate dielectric layer being on the first gate dielectric layer and separated from the channel region of the nanowire by the first gate dielectric layer, the second gate dielectric layer having a higher dielectric constant than the first gate dielectric layer;

a gate electrode around the channel region of the nanowire, the gate electrode being separated from the channel region of the nanowire by both the first gate dielectric layer and the second gate dielectric layer; and

wherein a portion of the first gate dielectric layer on an underside of the channel region of the nanowire extends below a top surface of the second layer.

2. The device of claim 1, wherein the first gate dielectric layer completely surrounds the nanowire in a first cross section taken normal to a line extending from the source region to the drain region, and the first gate dielectric layer does not completely surround the nanowire in a second cross section taken through the nanowire and parallel with a top surface of the substrate.

3. The device of claim 2, wherein a perimeter of the nanowire in the first cross section has a non-circular shape.

4. The device of claim 1, wherein the second dielectric layer has a dielectric constant greater than 8 and the first dielectric layer has a dielectric constant of 7 or less.

5. The device of claim 4, wherein the second gate dielectric layer comprises a material selected from the group consisting of tantalum silicon oxide (TaSiO_x), aluminum oxide (AlO_x), hafnium oxide (HfO₂), zirconium oxide (ZrO₂), and lanthanum oxide (La₂O₃), and the first gate dielectric layer comprises a material selected from the group consisting of aluminum silicate (AlSiO_x), silicon oxynitride (SiON), silicon dioxide (SiO₂) and silicon nitride (Si₃N₄).

6. The device of claim 4, wherein the first gate dielectric layer has a thickness between 2 and 15 nanometers, inclusive, and the second gate dielectric layer has a thickness between 0.5-3 nanometers, inclusive.

7. The device of claim 1, wherein the third material of the nanowire comprises an element from group III of the periodic table and further comprises an element from group V of the periodic table.

8. The device of claim 7, wherein the third material comprises In_xAs_1-x.

9. The device of claim 7, wherein the third material comprises In_xSb_1-x.

10. The device of claim 1, wherein a portion of the second gate dielectric layer below the underside of the channel region of the nanowire extends below the top surface of the second layer and a portion of the gate electrode below the underside of the channel region of the nanowire extends below the top surface of the second layer.

11. The device of claim 1, wherein the nanowire has a height and a width, and the height is approximately the same as the width.

12. The device of claim 1, further comprising a third layer above the nanowire and below the source and the drain.

13. A semiconductor device, comprising:

a semiconductor substrate comprising a first semiconductor material;

isolation regions on portions of the substrate but not completely covering the substrate;

a substrate extension region where a portion of the substrate not covered by an isolation region extends up past a bottom surface of the isolation region;

a second layer at least partially above the substrate extension region of the semiconductor substrate, the second layer having at least a portion above the bottom surface of the isolation region and below a top surface of the isolation region, the second layer comprising a second material different from the first semiconductor material;

a source region above the second layer, the source region having a top;

a drain region above the second layer, the drain region having a top, the drain region being laterally spaced from the source region;

a channel material region above the second layer, the channel material region having a length measured along a first axis that extends from the source region to the drain region, the length of the channel material region being great enough to span at least most of a lateral distance between the source region and the drain region, the channel material region having a height measured along a second axis extending up from the substrate, the channel material region having a width measured along a third axis substantially orthogonal to the first axis and the second axis, the length being greater than the height and being greater than the width, the channel material region comprising a third material different than the second material, the channel material region having a channel region, the channel material region having a top, the top of the channel material region being below the top of the source region and being below the top of the drain region;

a first gate dielectric layer around the channel region of the channel material region;

a second gate dielectric layer around the channel region of the channel material region, the second gate dielectric layer being on the first gate dielectric layer and separated from the channel region of the channel material region by the first gate dielectric layer, the second gate dielectric layer having a higher dielectric constant than the first gate dielectric layer;

a gate electrode around the channel region of the channel material region, the gate electrode being separated from the channel region of the channel material region by both the first gate dielectric layer and the second gate dielectric layer; and

wherein a portion of the first gate dielectric layer extends below a bottom of the channel region of the channel material region and extends below a top surface of the second layer, a portion of the second gate dielectric layer extends below the bottom of the channel region of the channel material region and extends below the top surface of the second layer, and a portion of the gate electrode extends below the bottom of the channel region of the channel material region and extends below the top surface of the second layer.

14. The device of claim 13, wherein the channel material region comprises a group III-V material.

15. The device of claim 14, wherein the third material comprises a material selected from the group consisting of In_xAs_1-x and In_xSb_1-x.

16. The device of claim 13, wherein the first gate dielectric layer completely surrounds the channel material region in a first cross section taken normal to a line extending from the source region to the drain region, and the first gate dielectric layer does not completely surround the channel material region in a second cross section taken through the channel material region and parallel with a top surface of the substrate.

17. The device of claim 13, wherein the second gate dielectric layer comprises a material selected from the group consisting of tantalum silicon oxide (TaSiOx), aluminum oxide (AlOx), hafnium oxide (HfO2), zirconium oxide (ZrO2), and lanthanum oxide (La2O3), and the first gate dielectric layer comprises a material selected from the group consisting of aluminum silicate (AlSiOx), silicon oxynitride (SiON), silicon dioxide (SiO2) and silicon nitride (Si3N4).

18. A semiconductor device, comprising:

a vertical arrangement of a plurality of group III-V material nanowires disposed above a substrate;

a gate stack disposed on and completely surrounding channel regions of each of the group III-V material nanowires, the gate stack comprising;

a first dielectric layer disposed on outer portions, but not an inner portion, of each of the channel regions;

a second, different, dielectric layer conformal with the first dielectric layer and disposed on the inner portion of each of the channel regions; and

a gate electrode disposed on the second dielectric layer;

a semiconductor layer disposed between the substrate and the bottom-most group III-V material nanowire, wherein a bottom portion of the gate stack is disposed on the semiconductor layer; and

source and drain regions disposed in or on each of the group III-V material nanowires, on either side of the gate stack.

19. The semiconductor device of claim 18, wherein the second dielectric layer has a higher dielectric constant than the first dielectric layer.

20. The semiconductor device of claim 19, wherein the second dielectric layer has a dielectric constant greater than approximately 8 and the first dielectric layer has a dielectric constant approximately in the range of 4-8.

21. The semiconductor device of claim 19, wherein the second dielectric layer comprises a material selected from the group consisting of tantalum silicon oxide (TaSiOx), aluminum oxide (AlOx), hafnium oxide (HfO2), zirconium oxide (ZrO2), and lanthanum oxide (La2O3), and the first dielectric layer comprises a material selected from the group consisting of aluminum silicate (AlSiOx), silicon oxynitride (SiON), silicon dioxide (SiO2) and silicon nitride (Si3N4).

22. The semiconductor structure of claim 18, wherein the first dielectric layer has a thickness approximately in the range of 2-15 nanometers, and the second dielectric layer has a thickness approximately in the range of 0.5-3 nanometers.