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Non-planar semiconductor device having active region with multi-dielectric gate stack

  • US 9,018,680 B2
  • Filed: 07/25/2014
  • Issued: 04/28/2015
  • Est. Priority Date: 09/27/2012
  • Status: Active Grant
First Claim
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1. A semiconductor device, comprising:

  • a semiconductor substrate comprising a first semiconductor material;

    a second layer above the semiconductor substrate, the second layer comprising a second material different from the first semiconductor material;

    a nanowire above the second layer, the nanowire comprising a third material different than the second material, the nanowire having a channel region;

    a source region to a first side of the channel region and having a top, the source region top being above a top of the nanowire;

    a drain region to a second side of the channel region, the second side of the channel region being opposite the first side, the drain region having a top, the drain region top being above the top of the nanowire;

    a first gate dielectric layer around the channel region of the nanowire;

    a second gate dielectric layer around the channel region of the nanowire, the second gate dielectric layer being on the first gate dielectric layer and separated from the channel region of the nanowire by the first gate dielectric layer, the second gate dielectric layer having a higher dielectric constant than the first gate dielectric layer;

    a gate electrode around the channel region of the nanowire, the gate electrode being separated from the channel region of the nanowire by both the first gate dielectric layer and the second gate dielectric layer; and

    wherein a portion of the first gate dielectric layer on an underside of the channel region of the nanowire extends below a top surface of the second layer.

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