Gas-diffusion barriers for MEMS encapsulation

• US 9,018,715 B2
• Filed: 11/30/2012
• Issued: 04/28/2015
• Est. Priority Date: 11/30/2012
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Quevy, Emmanuel P., Gu, Zhen, Howe, Roger T.
• Primary Examiner(s): Malsawma, Lex
• Application Number:
  US13/690,112
• Publication Number:
  US 20140151820A1
• Time in Patent Office: 879 Days
• Field of Search: 438/51
• US Class Current: 257/415
• CPC Class Codes: B81B 7/0038 using materials for controlling the level of pressure, contaminants or moisture inside of the package, e.g. getters
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/1461 MEMS

Abstract

A technique for forming an encapsulated microelectromechanical system (MEMS) device includes forming an integrated circuit using a substrate, forming a barrier using the substrate, and forming a MEMS device using the substrate. The method includes encapsulating the MEMS device in a cavity. The barrier is disposed between the integrated circuit and the cavity and inhibits the integrated circuit from outgassing into the cavity. The barrier may be substantially impermeable to gas migration from the integrated circuit.

Claims

1. A method comprising:

forming a barrier above a substrate incorporating an integrated circuit, the barrier comprising a metal oxide or a metal nitride;

forming a microelectromechanical system (MEMS) device including a portion suspended from the substrate; and

encapsulating the MEMS device in a cavity,

wherein the barrier is disposed between the integrated circuit and the cavity and inhibits the integrated circuit from outgassing into the cavity.

2. The method, as recited in claim 1, wherein the barrier is substantially impermeable to gas migration from the integrated circuit.

3. The method, as recited in claim 1, wherein the barrier has an oxygen transmission rate of less than approximately 5×

10<sup>−

3</sup> cc/m²/d.

4. The method, as recited in claim 1, wherein the barrier comprises an electrically insulating material.

5. The method, as recited in claim 1, further comprising:

forming a passivation layer above the integrated circuit, the barrier being formed on the passivation layer.

6. The method, as recited in claim 5, wherein the passivation layer comprises a SiN layer.

7. The method, as recited in claim 1, further comprising:

forming a plurality of passivation layers on the integrated circuit, the barrier being formed between individual passivation layers of the plurality of passivation layers.

8. The method, as recited in claim 1, wherein forming the barrier comprises:

forming a plurality of diffusion barrier layers; and

forming a passivation layer interposed between individual layers of the plurality of diffusion barrier layers.

9. The method, as recited in claim 1, wherein the barrier is formed at a temperature less than 450 degrees Celsius.

10. The method, as recited in claim 1, wherein the barrier is formed using atomic layer deposition or chemical vapor deposition.

11. A microelectromechanical system formed by the method of claim 1.

12. The method as recited in claim 1, wherein the barrier has a thickness t, where 10 nm ≦

t ≦

200 nm.

13. The method as recited in claim 1, wherein the barrier comprises at least one of an Al₂O₃ layer, a Ta₂O₅ layer, a ZrO₂ layer, a TiN layer, a TiO₂ layer, a SnO₂ layer, a ZnO layer, a HfO₂ layer, a NbN layer, a TaN layer, a WN layer, and a layer of amorphous silicon.

14. A method comprising:

forming a barrier above a substrate incorporating an integrated circuit;

forming a microelectromechanical system (MEMS) device including a portion suspended from the substrate; and

encapsulating the MEMS device in a cavity,

wherein the barrier is disposed between the integrated circuit and the cavity and inhibits the integrated circuit from outgassing into the cavity,

wherein the barrier has a water vapor transmission rate of approximately 5×

10<sup>−

3</sup> gm/m²/d or less.

15. The method as recited in claim 14, wherein the barrier has a thickness t, where 10 nm ≦

t ≦

200 nm.

16. The method as recited in claim 14, wherein the barrier comprises at least one of an Al₂O₃ layer, a Ta₂O₅ layer, a ZrO₂ layer, a TiN layer, a TiO₂ layer, a SnO₂ layer, a ZnO layer, a HfO₂ layer, a NbN layer, a TaN layer, a WN layer, and amorphous silicon.

17. The method as recited in claim 14, wherein the barrier comprises a layer of Al₂O₃ directly adjacent to a layer of SiN.

18. A method comprising:

forming a barrier above a substrate incorporating an integrated circuit, the barrier having a thickness t, where 10 nm ≦

t ≦

200 nm;

forming a microelectromechanical system (MEMS) device including a portion suspended from the substrate; and

encapsulating the MEMS device in a cavity,

wherein the barrier is disposed between the integrated circuit and the cavity and inhibits the integrated circuit from outgassing into the cavity.

19. The method as recited in claim 18, wherein the barrier comprises at least one of an Al₂O₃ layer, a Ta₂O₅ layer, a ZrO₂ layer, a TiN layer, a TiO₂ layer, a SnO₂ layer, a ZnO layer, a HfO₂ layer, a NbN layer, a TaN layer, and a WN layer.

20. The method as recited in claim 18, wherein the barrier comprises amorphous silicon.