Thin film structure for high density inductors and redistribution in wafer level packaging

• US 9,018,750 B2
• Filed: 08/10/2012
• Issued: 04/28/2015
• Est. Priority Date: 08/11/2011
• Status: Active Grant

• Current Assignee: Huatian Technology (Kunshan) Electronics Co., Ltd
• Original Assignee: Flipchip International LLC (Tianshui Huatian Technology Company Limited)
• Inventors: Forcier, Robert, Scott, Douglas
• Primary Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US13/572,376
• Publication Number:
  US 20130037956A1
• Time in Patent Office: 991 Days
• Field of Search: 257/737, 257/738, 257/E23.021, 257/E23.069, 257/621, 257/735, 257/736, 257/750, 257/751, 257/753, 257761-763, 257/764, 257/780, 257/781, 438612-617, 438/648
• US Class Current: 257/698
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1461 MEMS

Abstract

Disclosed is a package that includes a wafer substrate and a metal stack seed layer. The metal stack seed layer includes a titanium thin film outer layer. A resist layer is provided in contact with the titanium thin film outer layer of the metal stack seed layer, the resist layer forming circuitry. A method for manufacturing a package is further disclosed. A metal stack seed layer having a titanium thin film outer layer is formed. A resist layer is formed so as to be in contact with the titanium thin film outer layer of the metal stack seed layer, and circuitry is formed from the resist layer.

Claims

1. A package, comprising:

a wafer substrate;

a metal stack seed layer comprising a titanium thin film outer layer; and

,

a resist layer in contact with said titanium thin film outer layer of said metal stack seed layer, said resist layer forming circuitry, wherein said circuitry comprises one or more embedded die structures.

2. The package according to claim 1, wherein said circuitry comprises wafer level redistribution circuitry.

3. The package according to claim 1, wherein said circuitry comprises one or more inductors.

4. The package according to claim 1, wherein said circuitry comprises one or more antennas.

5. The package according to claim 1, wherein the package comprises flip chip packaging.

6. The package according to claim 1, wherein said circuitry comprises one or more interconnect structures.

7. The package according to claim 6, wherein said interconnect structures have a shape that is circular, rectangular, or octagonal.

8. The package according to claim 1, wherein said circuitry comprises one or more coil structures.

9. The package according to claim 1, wherein said circuitry comprises one or more MEMs structures.

10. The package according to claim 1, wherein said circuitry comprises one or more rotor structures.

11. The package according to claim 1, wherein said embedded die structures comprise multi-die, multi-discrete 3D packages where a wafer level package is embedded in a printed circuit, a module, a packaging substrate or a flex circuit.

12. The package according to claim 1, wherein said titanium thin film outer layer has a thickness of between 100 Angstroms and 1500 Angstroms.

13. The package according to claim 1, wherein said titanium thin film outer layer has a thickness of 250 Angstroms.

14. A package, comprising:

a wafer substrate;

a metal stack seed layer comprising a titanium thin film outer layer; and

a resist layer in contact with said titanium thin film outer layer of said metal stack seed layer, said resist layer forming circuitry, wherein said metal stack seed layer comprises an aluminum layer, a nickel vanadium layer, a copper layer, and said titanium thin film outer layer.

15. A method for manufacturing a package, comprising:

forming a metal stack seed layer having a titanium thin film outer layer;

forming a resist layer so as to be in contact with said titanium thin film outer layer of said metal stack seed layer; and

forming circuitry from said resist layer;

wherein said step of forming circuitry from said resist layer comprises;

patterning said resist layer; and

,

etching said resist layer to form circuitry.

16. The method for manufacturing a package according to claim 15, wherein said circuitry comprises wafer level redistribution circuitry.

17. The method for manufacturing a package according to claim 15, wherein said circuitry comprises one or more inductors.

18. The method for manufacturing a package according to claim 15, wherein said circuitry comprises one or more antennas.

19. The method for manufacturing a package according to claim 15, wherein the package comprises flip chip packaging.

20. The method for manufacturing a package according to claim 15, wherein said circuitry comprises one or more interconnect structures.

21. The method for manufacturing a package according to claim 20, wherein said interconnect structures have a shape that is circular, rectangular, or octagonal.

22. The method for manufacturing a package according to claim 15, wherein said circuitry comprises one or more coil structures.

23. The method for manufacturing a package according to claim 15, wherein said circuitry comprises one or more MEMs structures.

24. The method for manufacturing a package according to claim 15, wherein said circuitry comprises one or more rotor structures.

25. The method for manufacturing a package according to claim 15, wherein said titanium thin film outer layer is formed to be between 100 Angstroms and 1500 Angstroms thick.

26. The method for manufacturing a package according to claim 15, wherein said titanium thin film outer layer is formed to be 250 Angstroms thick.

27. The method for manufacturing a package according to claim 15, further comprising the step of attaching a contact sphere.

28. A method for manufacturing a package, comprising:

forming a metal stack seed layer having a titanium thin film outer layer;

forming a resist layer so as to be in contact with said titanium thin film outer layer of said metal stack seed layer; and

forming circuitry from said resist layer;

wherein said circuitry comprises one or more embedded die structures.

29. The method for manufacturing a package according to claim 28, wherein said embedded die structures comprise multi-die, multi-discrete 3D packages where a wafer level package is embedded in a printed circuit, a module, a packaging substrate or a flex circuit.

30. A method for manufacturing a package, comprising:

forming a metal stack seed layer having a titanium thin film outer layer;

forming a resist layer so as to be in contact with said titanium thin film outer layer of said metal stack seed layer; and

forming circuitry from said resist layer;

wherein said step of forming a metal stack seed layer comprises sputtering aluminum, nickel vanadium, copper and said titanium thin film outer layer.