Cu pillar bump with non-metal sidewall spacer and metal top cap

• US 9,018,758 B2
• Filed: 06/02/2010
• Issued: 04/28/2015
• Est. Priority Date: 06/02/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hwang, Chien Ling, Wu, Yi-Wen, Liu, Chung-Shi, Tsai, Hui-Jung
• Primary Examiner(s): Sarkar, Asok K
• Assistant Examiner(s): Yemelyanov, Dmitriy
• Application Number:
  US12/792,002
• Publication Number:
  US 20110298123A1
• Time in Patent Office: 1,791 Days
• Field of Search: 257/737, 257/E23.021, 257/E23.033, 257/E23.068, 257/E23.069, 257/E21.508, 438/613
• US Class Current: 257/734
• CPC Class Codes: C23C 14/34 Sputtering
• CPC Class Codes: C25D 5/022 using masking means
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/7688 by deposition over sacrificial masking layer, e.g. lift-off lift-off per se H01L21/0272
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03826 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03831 involving a chemical process, e.g. etching the bonding area
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/10126 Bump collar
• CPC Class Codes: H01L 2224/1145 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/11452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/11464 : Electroless plating
• CPC Class Codes: H01L 2224/11622 : Photolithography
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1354 : Coating
• CPC Class Codes: H01L 2224/13565 : Only outside the bonding interface of the bump connector
• CPC Class Codes: H01L 2224/16148 : the bump connector connecting to a bonding area protruding from the surface
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/81024 : Applying flux to the bonding area
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81447 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/81911 : Chemical cleaning, e.g. etching, flux
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/0104 : Zirconium [Zr]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A bump has a non-metal sidewall spacer on a lower sidewall portion of Cu pillar, and a metal top cap on a top surface and an upper sidewall portion of the Cu pillar. The metal top cap is formed by an electroless or immersion plating technique after the non-metal sidewall spacer formation.

Claims

1. An integrated circuit device, comprising:

a semiconductor substrate;

a pad over the semiconductor substrate;

a passivation layer over the pad and exposing at least a portion of the pad;

an under-bump-metallurgy (UBM) layer over the pad and the passivation layer;

a conductive pillar formed on the UBM layer, and having a top surface and a sidewall surface, wherein the sidewall surface has a first portion adjacent to the top surface and a second portion adjacent to the UBM layer, the first portion and the second portion are coplanar, and the first portion and the top surface are not coplanar;

a non-metal protection structure formed on the second portion of the sidewall surface of the conductive pillar; and

a metal cap layer formed on the top surface of the conductive pillar and extending to cover the first portion of the sidewall surface of the conductive pillar.

2. The integrated circuit device of claim 1, wherein the non-metal protection structure comprises a silicon nitride layer.

3. The integrated circuit device of claim 1, wherein the non-metal protection structure comprises a polyimide layer.

4. The semiconductor device of claim 1, wherein the UBM layer comprises:

a first UBM layer formed between the semiconductor substrate and the conductive pillar; and

a second UBM layer formed between the first UBM layer and the conductive pillar;

wherein the second UBM layer has a sidewall surface, and the first UBM layer has a surface region extending outwardly from the sidewall surface of the second UBM layer.

5. The integrated circuit device of claim 4, wherein the non-metal protection structure extends to cover the sidewall surface of the second UBM layer and the surface region of the first UBM layer.

6. The integrated circuit device of claim 4, wherein the first UBM layer comprises a titanium layer, and the second UBM layer comprises a copper layer.

7. The integrated circuit device of claim 1, wherein the metal cap layer comprises an electroless nickel (Ni) layer.

8. The integrated circuit device of claim 1, wherein the metal cap layer comprises an electroless palladium (Pd) layer.

9. The integrated circuit device of claim 1, wherein the metal cap layer comprises an immersion gold (Au) layer.

10. The integrated circuit device of claim 1, wherein the conductive pillar is a copper-containing pillar.

11. A packaging assembly, comprising:

a first substrate;

a pad over the first substrate;

a passivation layer over the pad and exposing at least a portion of the pad;

an under-bump-metallurgy (UBM) layer over the pad and the passivation layer;

a copper pillar formed over the UBM layer, and having a top surface portion, a first sidewall portion adjacent to the top surface portion, and a second sidewall portion adjacent to the first substrate, the first sidewall portion and the second sidewall portion being coplanar, and the first sidewall portion and the top surface portion are not coplanar;

a non-metal protection structure covering the second sidewall portion of the copper pillar;

a metal cap layer covering the top surface portion and the first sidewall portion of the copper pillar;

a second substrate; and

a joint solder layer formed between the second substrate and the metal cap layer.

12. The packaging assembly of claim 11, wherein the non-metal protection structure comprises a silicon nitride layer.

13. The packaging assembly of claim 11, wherein the non-metal protection structure comprises a polyimide layer.

14. The packaging assembly of claim 11, further comprising:

a first UBM layer formed between the first substrate and the copper pillar; and

a second UBM layer formed between the first UBM layer and the copper pillar;

wherein the second UBM layer has a sidewall surface, and the first UBM layer has a surface region extending outwardly from the sidewall surface of the second UBM layer.

15. The packaging assembly of claim 14, wherein the non-metal protection structure extends to cover the sidewall surface of the second UBM layer and the surface region of the first UBM layer.

16. The packaging assembly of claim 14, wherein the first UBM layer comprises a titanium layer, and the second UBM layer comprises a copper layer.

17. The packaging assembly of claim 11, wherein the metal cap layer comprises an electroless nickel (Ni) layer.

18. The packaging assembly of claim 17, wherein the metal cap layer comprises an electroless palladium (Pd) layer formed on the electroless Ni layer.

19. The packaging assembly of claim 18, wherein the metal cap layer comprises an immersion gold (Au) layer formed on the electroless Pd layer.

20. The packaging assembly of claim 17, wherein the metal cap layer comprises an immersion gold (Au) layer formed on the electroless Ni layer.