Semiconductor device bonding with stress relief connection pads

• US 9,018,762 B2
• Filed: 04/19/2013
• Issued: 04/28/2015
• Est. Priority Date: 12/25/2006
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Kasai, Masaki, Okumura, Hiroshi
• Primary Examiner(s): CAMPBELL, SHAUN M
• Application Number:
  US13/866,049
• Publication Number:
  US 20130234327A1
• Time in Patent Office: 739 Days
• Field of Search: 257/738
• US Class Current: 257/738
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05007 comprising a core and a coating
• CPC Class Codes: H01L 2224/05018 being a conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05082 Two-layer arrangements
• CPC Class Codes: H01L 2224/05541 Structure
• CPC Class Codes: H01L 2224/05547 comprising a core and a coating
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05557 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/05559 non conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13006 Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01002 : Helium [He]
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

An inventive semiconductor device includes: a semiconductor chip; an internal pad provided on a surface of the semiconductor chip for electrical connection; a surface protective film covering the surface of the semiconductor chip and having a pad opening from which the internal pad is exposed; a stress relief layer provided on the surface protective film and having an opening portion through which the internal pad exposed from the pad opening is exposed; a connection pad including an anchor buried in the pad opening and the opening portion and connected to the internal pad, and a projection provided integrally with the anchor as projecting on the stress relief layer, the projection having a width greater than an opening width of the opening portion; and a metal ball provided for external electrical connection as covering the projection of the connection pad.

Claims

1. A semiconductor device, comprising:

a semiconductor chip;

an internal pad provided on a surface of the semiconductor chip for electrical connection;

a surface protective film covering the surface of the semiconductor chip and having a pad opening from which the internal pad is exposed;

a stress relief layer provided on the surface protective film and having an opening portion through which the internal pad exposed from the pad opening is exposed;

a bump underlying layer that covers the internal pad, an interior surface of the opening portion of the stress relief layer and a surface of the stress relief layer around the opening portion;

a connection pad made of copper, the connection pad including a copper anchor buried in the pad opening and the opening portion and connected to the internal pad via the bump underlying layer, and a copper projection provided integrally with the anchor and projecting on the stress relief layer, the projection having a width greater than an opening width of the opening portion and a width of the internal pad, the projection being opposed to the surface of the stress relief layer via the bump underlying layer, the projection having a distal surface that faces away from the stress relief layer, and which has a first portion disposed directly aligned with the anchor and a second portion over the stress relief layer, the first portion and the second portion collectively defining the entire distal surface of the projection as being flat and being at a common level, the distal surface and a side surface of the projection being rough, a boundary surface between the projection and the bump underlying layer as being smooth; and

a metal ball provided for external electrical connection and covering the projection of the connection pad.

2. The semiconductor device according to claim 1, wherein the projection of the connection pad is cylindrical.

3. The semiconductor device according to claim 1, wherein the distal surface and the side surface are in direct physical contact with the metal ball.

4. The semiconductor device according to claim 3, wherein the metal ball covers the entire distal surface and side surface.

5. The semiconductor device according to claim 1, wherein the projection of the connection pad has an upper projection portion formed on the bump underlying layer and a lower projection portion integrally formed on the upper projection portion.

6. The semiconductor device according to claim 1, further comprising a metal flange provided around the projection of the connection pad.

7. The semiconductor device according to claim 6, wherein the metal flange is made of copper.

8. The semiconductor device according to claim 1, wherein the side surface of the projection is flush with a side surface of the bump underlying layer.

9. The semiconductor device according to claim 1, provided as the wafer-level chip-scale package.

10. The semiconductor device according to claim 1, wherein the semiconductor chip has a generally rectangular shape as seen in plan.

11. The semiconductor device according to claim 10, wherein the internal pads are arranged in two rows as seen in plan along an outer periphery of the semiconductor chip.