Chip package

• US 9,018,774 B2
• Filed: 09/09/2008
• Issued: 04/28/2015
• Est. Priority Date: 03/30/2001
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Lee, Jin-Yuan, Huang, Ching-Cheng, Lin, Mou-Shiung
• Primary Examiner(s): VU, HUNG K
• Application Number:
  US12/206,751
• Publication Number:
  US 20090008778A1
• Time in Patent Office: 2,422 Days
• Field of Search: 257/678, 257/778, 257/781, 257/E21.508, 257/738, 257/E21.503, 257/E21.511, 257/E23.021, 438/106, 438/108, 438/614
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/293 Organic, e.g. plastic
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure.

Claims

1. A chip package comprising:

a substrate;

a die coupled to said substrate, wherein a first opening through said substrate is coupled to said die, wherein said die comprises a contact pad and a passivation layer having a first surface on said die and an opposing second surface, wherein a second opening in said passivation layer exposes a contact point of said contact pad, and said contact point is within said second opening;

an adhesive material directly on and coupled to said second surface of said passivation layer and between said substrate and said die, said passivation layer separating said adhesive layer from said contact pad;

a conductive interconnect within an opening of said adhesive material and coupled to said contact point exposed by said first opening; and

a molding material coupled to said die, to said substrate and at first and second sides of said die, wherein said molding material has a first sawed sidewall and a second sawed sidewall substantially parallel with said first sawed sidewall.

2. The chip package of claim 1, wherein said contact pad comprises copper.

3. The chip package of claim 1, wherein said die further comprises a conductive layer, wherein said conductive layer is coupled to said contact point through said second opening, wherein said conductive interconnect is coupled to said contact point further through said conductive layer.

4. The chip package of claim 3, wherein said conductive layer comprises copper.

5. The chip package of claim 3, wherein said conductive layer comprises nickel.

6. The chip package of claim 1, wherein said molding material comprises a polymer.

7. The chip package of claim 1, wherein said substrate comprises bismaleimide triazine (BT).

8. The chip package of claim 1, wherein said contact pad comprises aluminum.

9. A chip package comprising:

a substrate;

a die coupled to said substrate, wherein a first opening through said substrate is coupled to said die, wherein said die comprises a copper layer, a conductive pad and a separating layer having a first surface on said die and an opposing second surface, wherein a second opening in said separating layer exposes a first contact point of said copper layer, wherein said conductive pad is coupled to said first contact point through said second opening, wherein a second contact point of said conductive pad is exposed by said first opening;

an adhesive material directly on and coupled to said second surface of said separating layer and between said substrate and said die, wherein said separating layer separates said adhesive layer from said conductive pad;

a conductive interconnect within an opening of said adhesive material and coupled to said second contact point exposed by said first opening; and

a molding material coupled to said substrate and at first and second sides of said die, wherein said molding material has a first outer sidewall and a second outer sidewall substantially parallel with said first outer sidewall.

10. The chip package of claim 9, wherein said conductive pad comprises copper.

11. The chip package of claim 9, wherein said conductive pad comprises nickel.

12. The chip package of claim 9, wherein said molding material comprises a polymer.

13. The chip package of claim 9, wherein said substrate comprises bismaleimide triazine (BT).

14. The chip package of claim 9, wherein said conductive pad is coupled to said first contact point and coupled to said separating layer.

15. A chip package comprising:

a ball-grid-array (BGA) substrate;

a die coupled to said BGA substrate, wherein a first opening through said BGA substrate is coupled to said die, wherein said die comprises a contact pad and a passivation layer having a first surface on said die and an opposing second surface, wherein a second opening in said passivation layer exposes a contact point of said contact pad, and said contact point is within said second opening;

an adhesive material directly on and coupled to said second surface of said passivation layer and between said BGA substrate and said die, said passivation layer separating said adhesive layer from said contact pad;

a conductive interconnect within an opening of said adhesive material and coupled to said contact point exposed by said first opening; and

a molding material coupled to said die, said top side of said BGA substrate and at first and second sides of said die, wherein said molding material has a first sawed sidewall and a second sawed sidewall substantially parallel with said first sawed sidewall.

16. The chip package of claim 15, wherein said contact pad comprises copper.

17. The chip package of claim 15, wherein said die further comprises a conductive layer at said bottom side of said die, wherein said conductive layer is coupled to said contact point through said second opening, wherein said conductive interconnect is coupled to said contact point further through said conductive layer.

18. The chip package of claim 17, wherein said conductive layer comprises copper.

19. The chip package of claim 17, wherein said conductive layer comprises nickel.

20. The chip package of claim 15, wherein said molding material comprises a polymer.

21. The chip package of claim 15, wherein said BGA substrate comprises bismaleimide triazine (BT).

22. The chip package of claim 15, wherein said contact pad comprises aluminum.

23. A chip package comprising:

a die comprising a contact pad and a passivation layer, wherein an opening in said passivation layer exposes a contact point of said contact pad, wherein all of said passivation layer is coupled to a first portion of said die, wherein said contact pad comprises copper;

a conductive layer coupled to said passivation layer and said contact point, wherein said conductive layer is coupled to said contact point within said opening;

a solder ball coupled between said die and a substrate within an opening of an adhesive layer, wherein said solder ball is coupled to said contact point through said conductive layer; and

a molding material at first and second sides of said die, wherein said molding material has a first outer sidewall and a second outer sidewall substantially parallel with said first outer sidewall.

24. The chip package of claim 23, wherein said molding material comprises a polymer.

25. The chip package of claim 23, wherein said conductive layer comprises copper.

26. The chip package of claim 23, wherein said solder ball comprises a tin-silver alloy.

27. The chip package of claim 23, wherein said molding material comprises a first portion coupled to said first side of said die, a second portion coupled to said second side of said die and a third portion coupled to said die and between said first and second portions, wherein said first, second and third portions continuously extend over said die.

28. The chip package of claim 23, wherein said conductive layer comprises nickel.

29. A chip package comprising:

a substrate having a first opening through said substrate;

a die coupled to said substrate, wherein said die comprises a contact pad and a passivation layer, wherein said first opening through said substrate exposes said die, and wherein a second opening in said passivation layer exposes a contact point of said contact pad;

a solder ball coupled between said die and said substrate within an opening of an adhesive layer, said solder ball coupled to said contact point of said contact pad of said die through said second opening in said passivation layer; and

a molding material coupled to at least first and second sides of said die, wherein said molding material has a first outer sidewall and a second outer sidewall substantially parallel with said first outer sidewall of said molding material, in which contact between said molding material and said solder ball is avoided.

30. The chip package of claim 29, wherein said substrate comprises a ball-grid-array (BGA) substrate.

31. The chip package of claim 29, wherein said substrate has a first outer sidewall substantially coplanar with said first outer sidewall of said molding material and a second outer sidewall substantially coplanar with said second outer sidewall of said molding material.

32. The chip package of claim 29, wherein said die comprises a copper pad coupled to said die and to said solder ball.

33. The chip package of claim 29, wherein said die comprises an aluminum-containing pad coupled to said die and to said solder ball.

34. The chip package of claim 29, wherein a conductive layer is coupled to said die and to said passivation layer and said contact point, wherein said conductive layer is coupled to said contact point through said second opening, wherein said solder ball is coupled to said conductive layer.

35. The chip package of claim 34, wherein said conductive layer comprises copper.

36. The chip package of claim 34, wherein said conductive layer comprises nickel.

37. The chip package of claim 34, wherein said contact pad comprises copper.

38. The chip package of claim 34, wherein said contact pad comprises aluminum.

39. The chip package of claim 29, wherein said solder ball comprises a tin-silver alloy.

40. The chip package of claim 29, wherein said solder ball comprises tin.

41. A chip package comprising:

a substrate having a first opening through said substrate;

a die coupled to said substrate, said die comprising a contact pad and a passivation layer wherein said first opening through said substrate exposes said die, wherein a second opening in said passivation layer exposes a contact point of said contact pad, wherein all of said passivation layer is coupled to a portion of said die;

a conductive layer coupled to said passivation layer and to said contact point, wherein said conductive layer is coupled to said contact point through said second opening;

a solder ball coupled between said die and said substrate within an opening of an adhesive layer, wherein said solder ball is coupled to said contact point through said conductive layer; and

a molding material coupled to said die at first and second sides of said die, wherein said molding material has a first outer sidewall and a second outer sidewall substantially parallel with said first outer sidewall, wherein said molding material comprises a first portion coupled to said first side of said die, a second portion coupled to said second side of said die and a third portion coupled to said die and between said first and second portions, wherein said first, second and third portions continuously extend over said die, in which contact between said molding material and said solder ball is avoided.

42. The chip package of claim 41, wherein said molding material comprises a polymer.

43. The chip package of claim 41, wherein said conductive layer comprises copper.

44. The chip package of claim 41, wherein said conductive layer comprises nickel.

45. The chip package of claim 41, wherein said solder ball comprises a tin-silver alloy.

46. The chip package of claim 41 further comprising a ball- gridarray (BGA) substrate coupled to said die and said molding material.

47. A chip package comprising:

a substrate having a first opening through said substrate;

a die coupled to said substrate, said die comprising a first conductive layer, a second conductive layer and a passivation layer, wherein said first opening through said substrate exposes said die, wherein a second opening in said passivation layer exposes a first contact point of said first conductive layer, wherein said second conductive layer is coupled to said first contact point through said second opening;

a first polymer layer comprising a first portion coupled to said die and a second portion extending beyond a boundary of said die, wherein a third opening through said first polymer layer is coupled to a second contact point of said second conductive layer, in which contact between said first polymer layer and said first conductive layer is avoided; and

a conductive interconnect within an opening of said first polymer layer and coupled to said second contact point through said third opening.

48. The chip package of claim 47, wherein said third opening has a width greater than that of said second opening.

49. The chip package of claim 47, wherein said third opening is coupled to said second opening.

50. The chip package of claim 47, wherein said third opening is laser drilled.

51. The chip package of claim 47, wherein said first conductive layer comprises copper.

52. The chip package of claim 47, wherein said first conductive layer comprises aluminum.

53. The chip package of claim 47, wherein said second conductive layer comprises copper.

54. The chip package of claim 47, wherein said second conductive layer comprises nickel.

55. The chip package of claim 47 further comprising a second polymer layer comprising a first portion coupled to said die and a second portion extending beyond a boundary of said die.

56. A chip package comprising:

a substrate having a first opening through said substrate;

a die coupled to said substrate, said die comprising a copper layer, a first separating layer, a conductive layer and a second separating layer, wherein said first opening through said substrate exposes said die, wherein a second opening in said first separating layer exposes a first contact point of said copper layer, wherein said conductive layer is coupled to said first contact point through said second opening, wherein said second separating layer is coupled to a surface and a sidewall of said conductive layer and coupled to said first separating layer, wherein a third opening in said second separating layer is coupled to a second contact point of said conductive layer;

a first polymer layer comprising a first portion coupled to said die and a second portion extending beyond a boundary of said die, in which contact between said first polymer layer and said conductive layer is avoided; and

a conductive bump on said conductive layer and in said first polymer layer, wherein said conductive bump is coupled to said conductive layer, wherein said conductive bump is coupled to said second opening.

57. The chip package of claim 56, wherein said conductive layer comprises copper.

58. The chip package of claim 56, wherein said conductive layer comprises nickel.

59. The chip package of claim 56 further comprising a second polymer layer coupled to said die and at first and second sides of said die.

60. The chip package of claim 56 further comprising a molding material coupled to said die and at first and second sides of said die.

61. The chip package of claim 56, wherein said conductive bump comprises tin.

62. The chip package of claim 56, wherein said conductive bump comprises a tin-silver alloy.

63. The chip package of claim 56, wherein said conductive bump contacts said first polymer layer.