Method and system to verify the reliability of electronic devices

• US 9,018,965 B2
• Filed: 11/26/2009
• Issued: 04/28/2015
• Est. Priority Date: 12/29/2008
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Ricci, Raffaele
• Primary Examiner(s): Nguyen, Tung X
• Assistant Examiner(s): LE, SON T
• Application Number:
  US13/142,528
• Publication Number:
  US 20110267081A1
• Time in Patent Office: 1,979 Days
• Field of Search: 324/110, 324/452, 324/527, 324/555, 324/600, 324/72, 32475005-75007, 324/537, 324/750.01, 324/754.19, 324/762.01, 324/762.02, 702 57- 58, 702/124, 361/56
• US Class Current: 324/750.01
• CPC Class Codes: G01R 31/002 where the device under test is an electronic circuit
• CPC Class Codes: G01R 31/2849 Environmental or reliability testing, e.g. burn-in or validation tests of individual semiconductors G01R31/2642; of printed circuits boards G01R31/2817; of IC's G01R31/2855

Abstract

To verify robustness with respect to electrical overstresses of an electronic circuit under test, the latter is exposed to electrical overstresses, and the behavior thereof is monitored. In particular, both the testing of the electronic circuit in dynamic conditions is performed by causing it to be traversed by the currents that characterize operation thereof, and by exposing at least one supply line of the electronic circuit under test to electrical overstresses and the testing of the electronic circuit under test in static conditions, without causing it to be traversed by the currents that characterize operation thereof, and by exposing to electrical overstresses both the supply and the input and/or output lines of the electronic circuit under test. The device for generating the overstresses can be mounted on a circuit board, which can be coupled as daughter board to a mother board, on which the electronic circuit under test is mounted.

Claims

1. A method of testing an electronic circuit comprising:

operating the electronic circuit while exposing the electronic circuit to electrical overstresses;

generating the electrical overstresses as an electrical pulse train, with amplitudes, durations, pulse widths, pulse train frequency, and overshoot voltages of the electrical pulse train being settable in real time;

simultaneously superimposing the electrical overstresses on a plurality of different supply voltages of the electronic circuit, each supply voltage being subject to a respective electrical overstress different from the electrical overstress superimposed on other supply voltages; and

monitoring operation of the electronic circuit after exposure to the electrical overstresses.

2. The method of claim 1, wherein exposing the electronic circuit to the electrical overstresses comprises exposing at least one of the plurality of different supply voltages and an input/output line of the electronic circuit to the electrical overstresses.

3. The method of claim 1, further comprising synchronously applying test stimuli to the electronic circuit while exposing the electronic circuit to the electrical overstresses.

4. The method of claim 1, further comprising asynchronously applying test stimuli to the electronic circuit while exposing the electronic circuit to the electrical overstresses.

5. A method of testing an electronic circuit comprising:

operating the electronic circuit while exposing a plurality of different supply voltages and an input/output line thereof to electrical overstresses by simultaneously superimposing the electrical overstresses on the plurality of different supply voltages and the input/output line of the electronic circuit in real time, each supply voltage being subject to a respective electrical overstress different from the electrical overstress superimposed on other supply voltages; and

monitoring operation of the electronic circuit after exposure to the electrical overstresses;

the electrical overstresses comprising an electrical pulse train having a settable amplitude, a settable duration, a settable pulse width, a pulse train frequency, and a settable overshoot voltage.

6. The method of claim 5, further comprising synchronously applying test stimuli to the electronic circuit while exposing the electronic circuit to the electrical overstresses.

7. The method of claim 5, further comprising asynchronously applying test stimuli to the electronic circuit while exposing the electronic circuit to the electrical overstresses.

8. A system for testing an electronic circuit comprising:

a motherboard to be coupled to the electronic circuit;

a daughterboard to be coupled to the motherboard and configured to

set amplitudes, durations, pulse widths, pulse train frequencies, and overshoot voltages of an electrical pulse train in real time, and

expose the electronic circuit to electrical overstresses while the electronic circuit is operating by simultaneously superimposing the electric pulse train on a plurality of different supply voltages of the electronic circuit, each supply voltage being subject to a respective electrical overstress different from the electrical overstress superimposed on other supply voltages; and

a circuit monitor configured to monitor operation of the electronic circuit after exposure thereof to the electrical overstresses.

9. The system claim 8, wherein the electronic circuit has an input/output line;

and wherein the daughterboard is configured to expose the electronic circuit to the electrical overstresses by exposing at least one of the plurality of different supply voltages and the input/output line to the electrical overstresses.

10. The system of claim 8, wherein the motherboard is configured to synchronously apply test stimuli to the electronic circuit while the daughter board exposes the electronic circuit to the electrical overstresses.

11. The system of claim 8, wherein the motherboard is configured to asynchronously apply test stimuli to the electronic circuit while the daughter board exposes the electronic circuit to the electrical overstresses.