Area-efficient physically unclonable function circuit architecture

• US 9,018,972 B1
• Filed: 05/31/2013
• Issued: 04/28/2015
• Est. Priority Date: 06/04/2012
• Status: Active Grant

• Current Assignee: National Technology & Engineering Solutions Of Sandia LLC (Honeywell International Inc.)
• Original Assignee: Sandia Corporation (Martin Marietta Corporation)
• Inventors: Gurrieri, Thomas, Hamlet, Jason, Bauer, Todd, Helinski, Ryan, Pierson, Lyndon G.
• Primary Examiner(s): CRAWFORD, JASON
• Application Number:
  US13/906,628
• Time in Patent Office: 697 Days
• Field of Search: 326/8
• US Class Current: 326/8
• CPC Class Codes: H03K 19/003 Modifications for increasing the reliability for protection

Abstract

Generating a physically a physically unclonable function (“PUF”) circuit value includes comparing each of first identification components in a first bank to each of second identification components in a second bank. A given first identification component in the first bank is not compared to another first identification component in the first bank and a given second identification component in the second bank is not compared to another second identification component in the second bank. A digital bit value is generated for each comparison made while comparing each of the first identification components to each of the second identification components. A PUF circuit value is generated from the digital bit values from each comparison made.

Claims

1. A method of generating a physically unclonable function (“

PUF”

) circuit value comprising;

comparing each of first identification components in a first bank to each of second identification components in a second bank, wherein a given first identification component in the first bank is not compared to another first identification component in the first bank, and wherein a given second identification component in the second bank is not compared to another second identification component in the second bank each of the first identification components including a first capacitor and each of the second identification components including a second capacitor;

generating a digital bit value for each comparison made while comparing each of the first identification components to each of the second identification components; and

generating a PUF circuit value from the digital bit values generated from each comparison made, wherein comparing each of the first identification components to each of the second identification components includes;

unbalancing charge on the first capacitor and the second capacitor;

rebalancing the charge on the first capacitor and the second capacitor, after unbalancing the charge; and

generating an output voltage representative of a difference between the first capacitor and the second capacitor, wherein generating the digital bit value includes comparing the output voltage to a reference voltage.

2. The method of claim 1, wherein n components is a sum of the first identification components and the second identification components, and wherein comparing each of the first identification components in the first bank to each of the second identification components in the second bank allows (n/2)² of the comparisons and (n/2)² of the digital bit values, wherein the digital bit values are uncorrelated.

3. The method of claim 1 further comprising:

generating a count value for each of the first identification components and each of the second identification components by individually coupling each of the first identification components and each of the second identification components as an integrating element of an oscillator and counting oscillations of the oscillator in a specified integration period,

wherein comparing each of the first identification components to each of the second identification components includes comparing the count value for each of the first identification components and each of the second identification components.

4. The method of claim 3 further comprising:

storing the count value for each of the first identification components and each of the second identification components in a memory.

5. The method of claim 1, wherein each of the first identification components and each of the second identification components are a same circuit having random manufacturing variances.

6. A non-transitory machine-accessible storage medium that provides instructions that, when executed by a machine, will cause the machine to perform operations comprising:

comparing each of first electronic components in a first bank to each of the second electronic components in a second bank, wherein a given first identification component in the first bank is not compared to another first identification component in the first bank, and wherein a given second identification component in the second bank is not compared to another second identification component in the second bank;

generating a digital bit value for each comparison made while comparing each of the first electronic components to each of the second electronic components; and

generating a PUF circuit value from the digital bit values generated from each comparison made, wherein n components is a sum of the first identification components and the second identification components, and wherein comparing each of the first identification components in the first bank to each of the second identification components in the second bank allows (n/2)² of the comparisons and (n/2)² of the digital bit values, wherein the digital bit values are uncorrelated.

7. The non-transitory machine-accessible storage medium of claim 6, wherein each of the first electronic components consists of a first capacitor and each of the second electronic components consists of a second capacitor.

8. The non-transitory machine-accessible storage medium of claim 7, wherein comparing each of the first electronic components to each of the second electronic components includes:

unbalancing charge on the first capacitor and the second capacitor;

rebalancing the charge on the first capacitor and the second capacitor, after unbalancing the charge; and

generating an output voltage representative of a difference between the first capacitor and the second capacitor, wherein generating the digital bit value includes comparing the output voltage to a reference voltage.

9. The non-transitory machine-accessible storage medium of claim 6, further providing instructions that, when executed by the machine, will cause the machine to perform further operations, comprising:

generating a count value for each of the first identification components and each of the second identification components by individually coupling each of the first identification components and each of the second identification components as an integrating element of an oscillator and counting oscillations of the oscillator in a specified integration period,

wherein comparing each of the first identification components to each of the second identification components includes comparing the count value for each of the first identification components and each of the second identification components.

10. The non-transitory machine-accessible storage medium of claim 9, further providing instructions that, when executed by the machine, will cause the machine to perform further operations, comprising:

storing the count value for each of the first electronic components and each of the second electronic components in a memory.

11. The non-transitory machine-accessible storage medium of claim 6, wherein each of the first electronic components and each of the second electronic components are a same circuit having random manufacturing variances.

12. A physically unclonable function (“

PUF”

) circuit system comprising;

a first array of first identification components;

a second array of second identification components;

a connecting unit coupled between at least one input and the first and second arrays to selectably couple each of the first and second identification components to the at least one input; and

measurement circuitry coupled to the connecting unit to control which of the first identification components and the second identification components are coupled to the at least one input, wherein the measurement circuitry is coupled to the at least one input and configured to compare first values generated by the first identification components to second values generated by the second identification components and generate a digital bit value for each comparison of the first values to the second values, wherein the measurement circuitry includes logic circuitry coupled to the connecting unit to individually select the first identification components in the first array to couple to the at least one input and to individually select the second identification components in the second array to couple to the at least one input.

13. The PUF circuit system of claim 12, wherein each of the first identification components include a first capacitor and each of the second identification components include a second capacitor.

14. The PUF circuit system of claim 13, wherein the measurement circuitry includes:

an integrating oscillator coupled to the at least one input, wherein the logic circuitry includes a counter coupled to an oscillation output of the integrating oscillator to count oscillations of the integrating oscillator for a specified time period.

15. The PUF circuit system of claim 12, wherein each of the first identification components and each of the second identification components are a same circuit having random manufacturing variances.

16. The PUF circuit system of claim 12, wherein the measurement circuitry is not configured to generate the digital bit value for intra-array comparisons of first values to first values or second values to second values.

17. The PUF circuit system of claim 12, wherein n components is a sum of the first identification components and the second identification components, and wherein (n/2)² comparisons are made between the first values and the second values, generating (n/2)² of the digital bit values.