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Methods and systems to stress-program an integrated circuit

  • US 9,018,975 B2
  • Filed: 02/15/2013
  • Issued: 04/28/2015
  • Est. Priority Date: 02/15/2013
  • Status: Expired due to Fees
First Claim
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1. An apparatus, comprising:

  • a first integrated circuit block to assert complementary logic states at outputs of the first IC block based on complementary logic states at inputs of the first IC block;

    wherein the first IC block is stressed while complimentary logic states are applied to the inputs, to program the first IC block to assert pre-determined complementary logic states at the outputs upon de-activation of a reset control without assertion of the complementary logic states at the inputs.

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