Methods and systems to stress-program an integrated circuit

• US 9,018,975 B2
• Filed: 02/15/2013
• Issued: 04/28/2015
• Est. Priority Date: 02/15/2013
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Cowley, Nicholas P., Muthukaruppan, Ramnarayanan
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US13/768,411
• Publication Number:
  US 20140232430A1
• Time in Patent Office: 802 Days
• Field of Search: 326 38- 41, 365/96, 365/149, 365/189.05, 365/198.11, 365/189.14, 365/203, 365/205, 365/207, 365/208, 365/225.7
• US Class Current: 326/38
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: H03K 19/173 using elementary logic circuits as components

Abstract

Methods and systems to stress-program a first integrated circuit (IC) block to output a pre-determined value upon activation/reset, such as to support time-zero compensation/trimming. To program, the first block is configured with first-block program parameters to cause the first block to output a pre-determined value. The first block is stressed while configured with the first-block program parameters, to cause the first block to output the pre-determined value without the first-block program parameters. The first block may include a latch designed as a fully balance circuit and may be asymmetrically stressed to alter a characteristic of one path relative to another. The pre-determined value may be selected to compensate for process corner variations and/or other random variations.

Claims

1. An apparatus, comprising:

a first integrated circuit block to assert complementary logic states at outputs of the first IC block based on complementary logic states at inputs of the first IC block;

wherein the first IC block is stressed while complimentary logic states are applied to the inputs, to program the first IC block to assert pre-determined complementary logic states at the outputs upon de-activation of a reset control without assertion of the complementary logic states at the inputs.

2. The apparatus of claim 1, wherein the programmed first IC block is operable to assert complementary logic states at the outputs when complementary logic states are asserted at the inputs.

3. The apparatus of claim 1, wherein the first IC block is configured to assert the pre-determined complementary logic states at the outputs when the reset control is de-activated and the inputs are at a same voltage.

4. The apparatus of claim 1, wherein the first IC block includes:

buffer circuitry to assert complementary logic states at outputs of the buffer circuitry based on complementary logic states at the inputs of the first IC block; and

latch circuitry to latch the complementary logic states at the outputs of the buffer circuitry and assert the latched complementary logic states at the outputs of the first IC block;

wherein at least a portion of the buffer circuitry is stressed to program the buffer circuitry to assert the pre-determined complementary logic states at the outputs of the buffer circuitry upon de-activation of the reset control.

5. The apparatus of claim 4, wherein the buffer circuitry and the latch circuitry are asynchronous.

6. The apparatus of claim 1, wherein the first IC block includes:

first and second complementary circuit paths; and

reset circuitry to apply a reset voltage to complementary nodes of first and second complementary circuit paths when the reset control is active.

7. The apparatus of claim 1, wherein the first IC block is configured as a configuration register to provide at least one of the pre-determined complementary logic states as a programmed configuration register value upon de-activation of the reset control.

8. The apparatus of claim 7, wherein:

the first IC block and a second IC block are on a same IC die; and

the IC die is configurable to provide the second IC block with a selectable one of the programmed configuration register value from the first IC block and a default configuration register value.

9. The apparatus of claim 1, wherein:

the first IC block and a second IC block are on a same IC die; and

the second IC block is configured to receive at least one of the pre-determined complementary logic states from the first IC block as a pre-determined compensation value to compensate for one or more of process corner variations and random variations imparted by one or more IC blocks of the IC die.

10. The apparatus of claim 9, wherein the IC die further includes an internal bus to configure the second IC block during an evaluation, and wherein the pre-determined value is based on the evaluation.

11. The apparatus of claim 10, wherein the IC die is configured to provide an updated compensation value to the second IC block over the internal bus after the pre-determined compensation value is provided to the second IC block.

12. A method, comprising:

asserting complementary logic states at inputs of a first integrated circuit (IC) block to cause the first IC block to assert pre-determined complementary logic states at outputs of the first IC block; and

stressing at least a portion of the first IC block while the complementary logic states are asserted at the inputs, to program the first IC block to assert the pre-determined complementary logic states upon de-activation of a reset control without assertion of the complementary logic states at the inputs.

13. The method of claim 12, further including:

configuring the first IC block to assert the pre-determined complementary logic states at the outputs when the reset control is de-activated and the inputs are at a same voltage.

14. The method of claim 12, wherein:

the first IC block includes buffer circuitry to assert complementary logic states at outputs of the buffer circuitry based on complementary logic states at the inputs of the first IC block;

the first IC block further include latch circuitry to latch the complementary logic states at the outputs of the buffer circuitry and assert the latched complementary logic states at the outputs of the first IC block; and

the stressing includes stressing at least a portion of the buffer circuitry to program the buffer circuitry to assert the pre-determined complementary logic states at the outputs of the buffer circuitry upon de-activation of the reset control.

15. The method of claim 12, further including:

configuring the first IC block as a configuration register to provide at least one of the pre-determined complementary logic states as a programmed configuration register value upon de-activation of the reset control.

16. The method of claim 15, wherein the first IC block and a second IC block are on a same IC die, the method further including:

configuring the IC die to provide the second IC block with a selectable one of the programmed configuration register value from the first IC block, and a default configuration register value.

17. The method of claim 12, wherein the first IC block and a second IC block are on a same IC die, the method further including:

configuring the first IC block to provide at least one of the pre-determined logic states to a second IC block as a pre-determined compensation value to compensate for one or more of process corner variations and random variations imparted by one or more IC blocks of the IC die.

18. The method of claim 17, wherein the IC die includes an internal bus, the method further including:

configuring the second IC block over the internal bus, evaluating a corresponding output parameter of the second IC block, and selecting the pre-determined value based on the evaluating.

19. The method of claim 18, further including:

configuring the IC die to provide an updated compensation value to the second IC block over the internal bus after the pre-determined compensation value is provided to the second IC block.

20. A non-transitory computer readable medium encoded with a computer program, including instructions to cause a processor to:

provide complementary logic states to inputs of a first integrated circuit (IC) block to cause the first IC block to assert pre-determined complementary logic states at outputs of the first IC block; and

control a system to stress at least a portion of the first IC block while the complementary logic states are asserted at the inputs, to program the first IC block to assert the pre-determined complementary logic states at the outputs upon de-activation of a reset control without assertion of the complementary logic states at the inputs.

21. The non-transitory computer readable medium of claim 20, wherein the first IC block includes buffer circuitry to assert complementary logic states at outputs of the buffer circuitry based on complementary logic states at the inputs of the first IC block, and latch circuitry to latch the outputs of the buffer circuitry and assert the latched outputs at the outputs of the first IC block, and wherein the computer readable medium further includes instructions to cause the processor to:

control the system to stress at least a portion of the buffer circuitry to cause the buffer circuitry to assert the pre-determined complementary logic states at the outputs of the buffer circuitry upon de-activation of the reset control.

22. The non-transitory computer readable medium of claim 20, wherein the first IC block and a second IC block are on a same IC die, and wherein the computer readable medium further includes instructions to cause the processor to:

configure the IC die to provide the second IC block with a selectable one of the programmed configuration register value from the first IC block, and a default configuration register value.

23. The non-transitory computer readable medium of claim 20, wherein the first IC block and a second IC block are on a same IC die, and wherein the computer readable medium further includes instructions to cause the processor to:

configure the first IC block to provide at least one of the pre-determined complementary logic states to the second IC block as a pre-determined compensation value to compensate for one or more of process corner variations and random variations imparted by one or more IC blocks of the IC die.

24. The non-transitory computer readable medium of claim 23, wherein the IC die further includes an internal bus, and wherein the computer readable medium further includes instructions to cause the processor to:

configure the second IC block over the internal bus, evaluate a corresponding output parameter of the second IC block, and select the pre-determined value based on the evaluating.

25. A system, comprising an integrated circuit (IC) die, including:

a processor and memory; and

compensation circuitry, to compensate for one or more of process corner variations and random variations imparted during manufacture of the IC die, based on a multiple-bit control word; and

metastable integrated circuitry to a output a random multiple-bit word when power is applied to the metastable integrated circuitry, wherein the metastable integrated circuitry is stress-programmable with one or more of voltage stress and temperature stress to transform the metastable integrated circuitry to stress-programmed integrated circuitry output a pre-determined multiple-bit control word to the compensation circuitry when power is applied to the stress-programmed integrated circuitry.

26. The system of claim 25, further including:

a user interface; and

a communication system to communicate between another communication system and one or more of the processor and the user interface.

27. The system of claim 26, wherein the communication system is configured to communicate with at least one of a wireless voice network and a wireless packet-based network.

28. The system of claim 27, configured as a battery powered portable device.