Integrated stacked power amplifier and RF switch architecture

• US 9,019,010 B2
• Filed: 05/22/2013
• Issued: 04/28/2015
• Est. Priority Date: 05/22/2012
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Costa, Julio
• Primary Examiner(s): NGUYEN, PATRICIA T
• Application Number:
  US13/900,077
• Publication Number:
  US 20130314163A1
• Time in Patent Office: 706 Days
• Field of Search: 330/295, 330/53, 330/124.R
• US Class Current: 330/53
• CPC Class Codes: H03F 2200/111 the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
• CPC Class Codes: H03F 2200/318 A matching circuit being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/408 the output amplifying stage of an amplifier comprising three power stages
• CPC Class Codes: H03F 2203/21157 A filter circuit being added at the output of a power amplifier stage
• CPC Class Codes: H03F 3/191 Tuned amplifiers H03F3/193, H03F3/195 take precedence
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H04B 1/0057 using diplexing or multiplexing filters for selecting the desired band

Abstract

Combination circuitry includes a relatively small preamplifier and includes hybrid circuitry. The hybrid circuitry is configured to perform mode switching while also performing some amplification, thus allowing the relatively small preamplifier to be smaller than a conventional power amplifier. In one embodiment, the hybrid circuitry includes first series portion configured to amplify when ON, a first shunt portion, a second series portion configured to amplify when ON, and a second shunt portion. The first series portion may include: a first transistor; a first variable impedance in communication with a gate of the first transistor, wherein the first variable impedance is configured to receive a first transistor control signal; a second transistor in series with the first transistor; and a second variable impedance in communication with a gate of the second transistor, wherein second variable impedance is configured to receive a second transistor control signal.

Claims

1. Combination circuitry comprising:

a preamplifier; and

hybrid circuitry including;

a first series portion configured to amplify upon receiving first series amplification signals,

a first shunt portion,

a second series portion configured to amplify upon receiving second series amplification signals, and

a second shunt portion.

2. The combination circuitry of claim 1, wherein the preamplifier is sized to provide substantially smaller power than a conventional amplifier matched with a conventional mode switch.

3. The combination circuitry of claim 1, wherein the preamplifier is sized to provide less than half of the power of a conventional amplifier matched with a conventional mode switch.

4. The combination circuitry of claim 1, wherein the hybrid circuitry is configured to provide more amplification than the preamplifier.

5. The combination circuitry of claim 2, wherein the preamplifier includes, in series:

an input matching network;

a first preamplifier transistor;

an interstage matching network; and

a second preamplifier transistor.

6. The combination circuitry of claim 1, wherein the combination circuitry is configured to operate in a first band upon receiving first band control signals, and is configured to operate in a second band upon receiving second band control signals.

7. The combination circuitry of claim 6, further configured such that, upon receiving first band control signals:

the first series portion amplifies;

the first shunt portion open circuits;

the second series portion open circuits; and

the second shunt portion short circuits.

8. The combination circuitry of claim 7, further configured such that, upon receiving second band control signals:

the first series portion open circuits;

the first shunt portion short circuits;

the second series portion amplifies; and

the second shunt portion open circuits.

9. The combination circuitry of claim 6, wherein the first series portion comprises:

a first transistor configured to receive a first transistor control signal; and

a second transistor in series with the first transistor and configured to receive a second transistor control signal.

10. The combination circuitry of claim 9, wherein the first transistor control signal is controlled independently from the second transistor control signal.

11. The combination circuitry of claim 6, wherein the first series portion comprises:

a first transistor;

a first variable impedance in communication with a gate of the first transistor, wherein the first variable impedance is configured to receive a first transistor control signal;

a second transistor in series with the first transistor;

a second variable impedance in communication with a gate of the second transistor, wherein the second variable impedance is configured to receive a second transistor control signal.

12. The combination circuitry of claim 1, wherein the first series portion comprises:

a first transistor configured to receive a first signal from the preamplifier; and

a second transistor configured to receive an amplified first signal from the first transistor.

13. The combination circuitry of claim 12, further comprising:

a controller and biasing network configured to send a first base control voltage to the first transistor and to send a second base control voltage to the second transistor, and

wherein the first transistor is configured to receive the first base control voltage, and

wherein the second transistor is configured to receive the second base control voltage.

14. The combination circuitry of claim 13, wherein second base control voltage is larger than the first base control voltage during a state when the first series portion is amplifying.

15. The combination circuitry of claim 12, further comprising:

a biasing network configured to send a first gate control voltage to the first transistor and to send a second gate control voltage to the second transistor, and

wherein the first transistor is configured to receive the first gate control voltage, and

wherein the second transistor is configured to receive the second gate control voltage independently from the first gate control voltage.

16. The combination circuitry of claim 15, wherein the second gate control voltage is greater than the first gate control voltage during a state when the first series portion is amplifying.

17. The combination circuitry of claim 12, further comprising:

a first variable impedance in communication with a gate of the first transistor and configured to receive the first gate control voltage; and

a second variable impedance in communication with a gate of the second transistor and configured to receive the second gate control voltage independently from the first gate control voltage.

18. The combination circuitry of claim 17, wherein the first variable impedance and the second variable impedance are substantially capacitive during the state when the first series portion is amplifying.

19. The combination circuitry of claim 1,

wherein the preamplifier includes an input matching network configured to receive an input signal and an input matching control voltage, and

wherein the hybrid circuitry includes a first output matching and biasing network in communication with the first series portion and with the first shunt portion, and includes a second output matching and biasing network in communication with the second series portion and the second series shunt.

20. The combination circuitry of claim 19, wherein the input matching network and the first output matching and biasing network are configured to present a desired impedance to elements external to the combination circuitry during a state in which the first series portion is amplifying.