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Sample and hold capacitance to digital converter

  • US 9,019,229 B2
  • Filed: 03/26/2010
  • Issued: 04/28/2015
  • Est. Priority Date: 03/26/2010
  • Status: Active Grant
First Claim
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1. A circuit for converting a quantity of charge into a digital value, the circuit comprising:

  • a sample and hold circuit configured to sample the quantity of charge from a capacitive sense matrix, the sample and hold circuit comprising an integrator that receives the quantity of charge from the capacitive sense matrix and converts the quantity of charge into a voltage; and

    an analog to digital converter that converts the voltage into a digital value,wherein the integrator comprises an operational amplifier, a capacitor connected between an input terminal and an output terminal of the operational amplifier, and an additional capacitor connected to the output terminal of the operational amplifier,wherein the sample and hold circuit further comprises a switch in parallel with the capacitor to reset the capacitor, and an additional switch in series between the input terminal of the operational amplifier and the additional capacitor to connect the additional capacitor in parallel with the capacitor,wherein the switch in parallel with the capacitor is connected to the output terminal of the operational amplifier;

    wherein the integrator is isolated from the capacitive sense matrix while the analog to digital converter converts the voltage into the digital value, andwherein the circuit further comprises at least one switch that resets a voltage across a capacitance between one or more selected lines and one or more selected columns of the capacitive sense matrix while the analog to digital converter converts the voltage into the digital value.

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