Systems and methods for data addressing in a storage device

• US 9,019,644 B2
• Filed: 05/23/2011
• Issued: 04/28/2015
• Est. Priority Date: 05/23/2011
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Han, Yang, Li, Zongwang, Yang, Shaohua, Chang, Wu
• Primary Examiner(s): Chery, Mardochee
• Application Number:
  US13/113,219
• Publication Number:
  US 20120300332A1
• Time in Patent Office: 1,436 Days
• Field of Search: 360/49, 360/55
• US Class Current: 360/49
• CPC Class Codes: G11B 20/1217 on discs
• CPC Class Codes: G11B 20/1833 by adding special lists or symbols to the coded information G11B20/1806, G11B20/1866 take precedence
• CPC Class Codes: G11B 20/1866 by interleaving G11B20/1809 takes precedence
• CPC Class Codes: G11B 2020/1222 ECC block, i.e. a block of error correction encoded symbols which includes all parity data needed for decoding
• CPC Class Codes: G11B 2020/1267 Address data
• CPC Class Codes: G11B 2020/1288 Formatting by padding empty spaces with dummy data, e.g. writing zeroes or random data when de-icing optical discs
• CPC Class Codes: G11B 2220/2516 Hard disks
• CPC Class Codes: G11B 5/012 Recording on, or reproducing or erasing from, magnetic disks G11B17/00, G11B19/00 take precedence
• CPC Class Codes: G11B 5/09 Digital recording

Abstract

Various embodiments of the present invention provide systems and methods for format efficient data storage. As an example, a data storage device is described that includes: a storage medium, a read/write head assembly, and a read channel circuit. The read/write head assembly is disposed in relation to the storage medium and operable to sense information corresponding to an encoded codeword. The read channel circuit is operable to receive the encoded codeword. The read channel circuit includes a missing symbols insertion circuit, a codeword de-scramble circuit, an address insertion circuit, and a data decoder circuit. The missing symbols insertion circuit, the codeword de-scramble circuit, and the address insertion circuit together are operable to pad a derivative of the encoded codeword with a plurality of symbols, to de-scramble the derivative of the encoded codeword, and to insert address information corresponding to the derivative of the encoded codeword to yield a modified encoded codeword. The data decoder circuit is operable to apply a data decoding algorithm to the modified encoded codeword to yield a decoded output.

Claims

1. A data storage device, the data storage device comprising:

a storage medium;

a read/write head assembly disposed in relation to the storage medium and operable to;

write a stored codeword to the storage medium; and

sense information corresponding to the stored codeword as an encoded codeword;

a read channel circuit operable to receive the encoded codeword, and including;

a missing symbols insertion circuit, a codeword de-scramble circuit, and an address insertion circuit that together are operable to pad a derivative of the encoded codeword with a plurality of symbols, to de-scramble the derivative of the encoded codeword, and to insert address information corresponding to the derivative of the encoded codeword to yield a modified encoded codeword; and

a data decoder circuit operable to apply a data decoding algorithm to the modified encoded codeword to yield a decoded output.

2. The data storage device of claim 1, the data storage device further comprising:

a data detector circuit operable to perform a data detection algorithm on the encoded codeword to yield a detected output, wherein the detected output is the derivative of the encoded codeword.

3. The data storage device of claim 2, wherein the detected output is a first detected output, the data detector circuit is a first data detector circuit, the codeword de-scramble circuit is a first codeword de-scramble circuit, and the data decoder circuit is a first data decoder circuit;

the data storage device further comprising;

a codeword scramble circuit operable to scramble the decoded output to yield a scrambled output;

a second data detector circuit operable to perform the data detection algorithm on the scrambled output to yield a second a detected output;

a second codeword de-scramble circuit operable to reverse the scrambling applied by the codeword scramble circuit to yield a de-scrambled output; and

a second data decoder circuit operable to apply the data decoding algorithm to the de-scrambled output yield a data output.

4. The data storage device of claim 1, the data storage device further comprises:

an address efficient data encoder circuit operable to calculate parity data based at least in part on a user data set and the address information, and to remove the address information to yield an address reduced codeword.

5. The data storage device of claim 4, the data storage device further comprises:

a codeword scramble circuit operable to scramble the address reduced codeword to yield the encoded codeword.

6. The data storage device of claim 1, wherein the missing symbols insertion circuit is operable to pad the derivative of the encoded codeword with a plurality of symbols to yield a padded codeword, wherein the codeword de-scramble circuit is operable to de-scramble the padded codeword to yield a de-scrambled codeword, and wherein the address insertion circuit is operable to insert the address information over one or more of the plurality of symbols to yield the modified encoded codeword.

7. The data storage device of claim 1, wherein the codeword de-scramble circuit is operable to perform both a global de-scrambling process and a local de-scrambling process.

8. The data storage device of claim 1, wherein the missing symbols insertion circuit is operable to pad the derivative of the encoded codeword with a plurality of symbols to yield a padded codeword, wherein the codeword de-scramble circuit is operable to perform both a local de-scramble process and a global de-scramble process on the padded codeword to yield a de-scrambled codeword, and wherein the address insertion circuit is operable to insert the address information over one or more of the plurality of symbols to yield the modified encoded codeword.

9. The data storage device of claim 1, wherein the missing symbols insertion circuit is operable to pad the derivative of the encoded codeword with a plurality of symbols to yield a padded codeword, wherein the address insertion circuit is operable to insert the address information over one or more of the plurality of symbols to yield an address modified codeword;

and the codeword de-scramble circuit is operable to de-scramble the padded codeword to yield a de-scrambled codeword.

10. An address efficient data read circuit, the data read circuit comprising:

a data detector circuit operable to process an encoded codeword to yield a detected codeword, wherein the encoded codeword includes parity information calculated based on both user data and address data, and wherein the encoded codeword has address data removed;

a combination of a missing symbols insertion circuit, a codeword de-scramble circuit, and an address insertion circuit that together are operable to receive the detected codeword, to pad the detected codeword with a plurality of symbols, to de-scramble the detected codeword, and to insert the address data corresponding to yield a modified codeword; and

a data decoder circuit operable to apply a data decoding algorithm to the modified codeword to yield a decoded output.

11. The circuit of claim 10, wherein the circuit is implemented as an integrated circuit.

12. The circuit of claim 10, wherein the circuit is implemented as part of a data storage device.

13. The circuit of claim 10, wherein the detected output is a first detected output;

wherein the data detector circuit is a first data detector circuit, the codeword de-scramble circuit is a first codeword de-scramble circuit, and the data decoder circuit is a first data decoder circuit; and

wherein the circuit further comprises;

a codeword scramble circuit operable to scramble the decoded output to yield a scrambled output;

a second data detector circuit operable to receive the scrambled output and to provide a corresponding second detected output;

a second codeword de-scramble circuit operable to reverse the scrambling applied by the codeword scramble circuit to yield a de-scrambled output; and

a second data decoder circuit operable to apply the data decoding algorithm to the de-scrambled output yield a data output.

14. The circuit of claim 10, wherein the missing symbols insertion circuit is operable to pad the derivative of the encoded codeword with a plurality of symbols to yield a padded codeword, wherein the codeword de-scramble circuit is operable to de-scramble the padded codeword to yield a de-scrambled codeword, and wherein the address insertion circuit is operable to insert the address information over one or more of the plurality of symbols to yield the modified encoded codeword.

15. The circuit of claim 10, wherein the missing symbols insertion circuit is operable to pad the derivative of the encoded codeword with a plurality of symbols to yield a padded codeword, wherein the codeword de-scramble circuit is operable to perform both a local de-scramble process and a global de-scramble process on the padded codeword to yield a de-scrambled codeword, and wherein the address insertion circuit is operable to insert the address information over one or more of the plurality of symbols to yield the modified encoded codeword.

16. The circuit of claim 10, wherein the missing symbols insertion circuit is operable to pad the derivative of the encoded codeword with a plurality of symbols to yield a padded codeword, wherein the address insertion circuit is operable to insert the address information over one or more of the plurality of symbols to yield an address modified codeword;

and the codeword de-scramble circuit is operable to de-scramble the padded codeword to yield a de-scrambled codeword.

17. The circuit of claim 10, the circuit further comprising:

an address efficient data encoder circuit operable to calculate parity data based at least in part on a user data set and address information, and to remove the address information to yield an address reduced codeword; and

a codeword scramble circuit operable to scramble the address reduced codeword to yield the encoded codeword.

18. The circuit of claim 10, wherein the data decoder circuit is a low density parity check decoder circuit.

19. The circuit of claim 10, wherein the data detector circuit is selected from a group consisting of:

a maximum a posteriori data detector circuit and a Viterbi algorithm detector circuit.

20. A method for format efficient data storage, the method comprising:

encoding a combination of a data set and an address to yield an encoded codeword;

removing the address from the encoded codeword to yield a reduced data set;

receiving the reduced data set;

padding a derivative of the reduced data set with a plurality of symbols, de-scrambling the derivative of the reduced data set, and inserting address information corresponding to the derivative of the reduced data set to yield a modified encoded codeword; and

decoding the modified encoded codeword to yield a decoded output.