State determination in resistance variable memory
First Claim
1. A method for sensing a resistance variable memory cell, comprising:
- applying an evaluation signal to a resistance variable memory cell in an array of resistance variable memory cells, the evaluation signal configured to cause the memory cell to switch from a first data state to a second data state at a threshold current;
sensing three or more responses from the memory cell responsive to the evaluation signal at three or more sample points;
determining a first delta between a first pair of the three or more responses;
determining a second delta between a second pair of the three or more responses;
determining an absolute difference between the first delta and the second delta; and
determining that the memory cell changes from the first data state to the second data state during application of the evaluation signal responsive to the absolute difference being above a predetermined threshold.
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Accused Products
Abstract
An evaluation signal is applied to a memory cell in an array of resistance variable memory cells. The evaluation signal is configured to cause the memory cell to switch from a first state to a second state. Responses from the memory cell are sensed at three or more sample points. Differences between the responses are determined. For example, with three sample points, a first delta is determined between the first two responses and a second delta is determined between the last two responses. A difference of deltas is determined as a difference between the first and second delta, or vice versa. It is determined that the memory cell changes from the first to the second state if the difference of deltas is above a threshold. It is determined that the memory cell remains in the second state if the difference of deltas is below the threshold.
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Citations
27 Claims
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1. A method for sensing a resistance variable memory cell, comprising:
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applying an evaluation signal to a resistance variable memory cell in an array of resistance variable memory cells, the evaluation signal configured to cause the memory cell to switch from a first data state to a second data state at a threshold current; sensing three or more responses from the memory cell responsive to the evaluation signal at three or more sample points; determining a first delta between a first pair of the three or more responses; determining a second delta between a second pair of the three or more responses; determining an absolute difference between the first delta and the second delta; and determining that the memory cell changes from the first data state to the second data state during application of the evaluation signal responsive to the absolute difference being above a predetermined threshold. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An apparatus, comprising:
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an array of resistance variable memory cells; and a controller coupled to the array and configured to; apply an evaluation signal to a resistance variable memory cell in the array of resistance variable memory cells; sense three or more responses from the resistance variable memory cell responsive to the evaluation signal at three or more sample points; determine a first delta between a first pair of the three or more responses; determine a second delta between a second pair of the three or more responses; determine an absolute difference between the first delta and the second delta; and determine whether the resistance variable memory cell changes from an initial data state to a different data state during application of the evaluation signal responsive to the absolute delta. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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20. A method for sensing a memory cell, comprising:
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applying an evaluation signal to a Spin Torque Transfer (STT) memory cell, the evaluation signal sufficient to cause the STT memory cell to switch from a first data state to a second data state at a threshold current, wherein the first data state is one of an anti-parallel state and a parallel state and the second data state is the other of the anti-parallel state and the parallel state; sensing responses of the STT memory cell to the evaluation signal by; sensing a first response at a first sample point; sensing a second response at a second sample point; and sensing a third response at a third sample point; determining a combined response as two times the second response less the first response and less the third response; determining that the STT memory cell was in the first data state if the combined response is greater than a predefined threshold; and determining that the STT memory cell was in the second data state if the combined response is less than the predefined threshold. - View Dependent Claims (21, 22)
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23. An apparatus, comprising:
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an array of resistance variable memory cells; and a controller coupled to the array and configured to determine a data state of a memory cell in the array of resistance variable memory cells by; applying an evaluation signal to the memory cell, the evaluation signal including a current that goes above a threshold current sufficient to cause the memory cell to switch from a first resistance to a second resistance; sensing a first response from the memory cell responsive to the evaluation signal at a first sample point; sensing a second response from the memory cell responsive to the evaluation signal at a second sample point; sensing a third response from the memory cell responsive to the evaluation signal at a third sample point; determining a first delta between the first response and the second response; determining a second delta between the second response and the third response; and determining whether the memory cell changes from the first resistance to the second resistance during application of the evaluation signal responsive to a difference between the first delta and the second delta. - View Dependent Claims (24, 25, 26, 27)
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Specification