State determination in resistance variable memory

• US 9,019,754 B1
• Filed: 12/17/2013
• Issued: 04/28/2015
• Est. Priority Date: 12/17/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bedeschi, Ferdinando
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US14/109,329
• Time in Patent Office: 497 Days
• Field of Search: 365/148, 365/158, 365/207
• US Class Current: 365/158
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: G11C 11/5607 using magnetic storage elements
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0035 Evaluating degradation, retention or wearout, e.g. by counting writing cycles
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0045 Read using current through the cell
• CPC Class Codes: G11C 2013/0047 Read destroying or disturbing the data
• CPC Class Codes: G11C 2013/0057 Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits

Abstract

An evaluation signal is applied to a memory cell in an array of resistance variable memory cells. The evaluation signal is configured to cause the memory cell to switch from a first state to a second state. Responses from the memory cell are sensed at three or more sample points. Differences between the responses are determined. For example, with three sample points, a first delta is determined between the first two responses and a second delta is determined between the last two responses. A difference of deltas is determined as a difference between the first and second delta, or vice versa. It is determined that the memory cell changes from the first to the second state if the difference of deltas is above a threshold. It is determined that the memory cell remains in the second state if the difference of deltas is below the threshold.

Claims

1. A method for sensing a resistance variable memory cell, comprising:

applying an evaluation signal to a resistance variable memory cell in an array of resistance variable memory cells, the evaluation signal configured to cause the memory cell to switch from a first data state to a second data state at a threshold current;

sensing three or more responses from the memory cell responsive to the evaluation signal at three or more sample points;

determining a first delta between a first pair of the three or more responses;

determining a second delta between a second pair of the three or more responses;

determining an absolute difference between the first delta and the second delta; and

determining that the memory cell changes from the first data state to the second data state during application of the evaluation signal responsive to the absolute difference being above a predetermined threshold.

2. The method of claim 1, further comprising determining that the memory cell remains in the first data state responsive to the absolute difference being below a predefined threshold.

3. The method of claim 1, wherein:

the memory cell is a Spin Torque Transfer (STT) memory cell;

the determining that the memory cell changes comprises determining the STT memory cell was in an anti-parallel state prior to applying the evaluation signal; and

the determining that the memory cell remains in the second data state comprises determining that the STT memory cell was in a parallel state prior to applying the evaluation signal.

4. The method of claim 3, further comprising applying a programming signal to the STT memory cell to return it to the anti-parallel state when the STT memory cell was determined to be in the anti-parallel state prior to applying the evaluation signal.

5. The method of claim 1, wherein:

the memory cell is a Spin Torque Transfer (STT) memory cell;

the determining that the memory cell changes comprises determining the STT memory cell was in a parallel state prior to applying the evaluation signal; and

the determining that the memory cell remains in the second data state comprises determining that the STT memory cell was in an anti-parallel state prior to applying the evaluation signal.

6. The method of claim 1, wherein:

the evaluation signal is a substantially linear current ramp in a range including the threshold current;

at least two of the three or more responses are sensed at sample points before the threshold current is reached; and

at least one of the three or more responses is sensed at a sample point after the threshold current is reached.

7. The method of claim 6, wherein the three or more responses are sensed with substantially equal time periods between each of the three or more sample points.

8. The method of claim 1, wherein:

the evaluation signal comprises three or more current levels wherein at least one of the three or more current levels is above the threshold current;

each of the three or more responses are sensed at sample points while a corresponding one of the three or more current levels is being applied to the memory cell;

at least two of the three or more responses are sensed at current levels below the threshold current; and

at least one of the three or more responses is sensed at a current level above the threshold current.

9. The method of claim 8, wherein the three or more current levels have substantially equal current deltas therebetween.

10. The method of claim 1, wherein one of the three or more responses is common to both the first pair and the second pair.

11. An apparatus, comprising:

an array of resistance variable memory cells; and

a controller coupled to the array and configured to;

apply an evaluation signal to a resistance variable memory cell in the array of resistance variable memory cells;

sense three or more responses from the resistance variable memory cell responsive to the evaluation signal at three or more sample points;

determine a first delta between a first pair of the three or more responses;

determine a second delta between a second pair of the three or more responses;

determine an absolute difference between the first delta and the second delta; and

determine whether the resistance variable memory cell changes from an initial data state to a different data state during application of the evaluation signal responsive to the absolute delta.

12. The apparatus of claim 11, wherein the controller is further configured to determine that the memory cell remains in the initial data state responsive to the absolute difference being below a predefined threshold.

13. The apparatus of claim 11, wherein the controller is configured to:

apply the evaluation signal as a substantially linear current ramp;

sense at least two of the three or more responses at sample points before the substantially linear current ramp reaches a threshold current sufficient to switch the memory cell from one data state to another data state; and

sense at least one of the three or more responses at a sample point after the threshold current is reached.

14. The apparatus of claim 13, wherein the three or more responses are sensed with substantially equal time periods between each of the three or more sample points.

15. The apparatus of claim 11, wherein the controller is configured to:

apply the evaluation signal at three or more current levels;

sense each of the three or more responses while a corresponding one of the three or more current levels is being applied to the memory cell;

sense at least two of the three or more responses at current levels equal to or below a threshold current sufficient to switch the resistance variable memory cell from one data state to another data state; and

sense at least one of the three or more responses at a current level above the threshold current.

16. The apparatus of claim 15, wherein the three or more current levels are at substantially equal current deltas therebetween.

17. The apparatus of claim 11, wherein the memory cell is a Spin Torque Transfer (STT) memory cell and the controller is further configured to determine the STT memory cell was in a parallel state prior to applying the evaluation signal if the STT memory cell does not change from the initial data state and determine the STT memory cell was in an anti-parallel state prior to applying the evaluation signal if the STT memory cell does change from the initial data state.

18. The apparatus of claim 17, wherein the controller is further configured to apply a programming signal to the STT memory cell to return it to the anti-parallel state when the STT memory cell was determined to be in the anti-parallel state.

19. The apparatus of claim 11, wherein the memory cell is a Spin Torque Transfer (STT) memory cell and the controller is further configured to determine the STT memory cell was in an anti-parallel state prior to applying the evaluation signal if the STT memory cell does not change from the initial data state and determine the STT memory cell was in a parallel state prior to applying the evaluation signal if the STT memory cell does change from the initial data state.

20. A method for sensing a memory cell, comprising:

applying an evaluation signal to a Spin Torque Transfer (STT) memory cell, the evaluation signal sufficient to cause the STT memory cell to switch from a first data state to a second data state at a threshold current, wherein the first data state is one of an anti-parallel state and a parallel state and the second data state is the other of the anti-parallel state and the parallel state;

sensing responses of the STT memory cell to the evaluation signal by;

sensing a first response at a first sample point;

sensing a second response at a second sample point; and

sensing a third response at a third sample point;

determining a combined response as two times the second response less the first response and less the third response;

determining that the STT memory cell was in the first data state if the combined response is greater than a predefined threshold; and

determining that the STT memory cell was in the second data state if the combined response is less than the predefined threshold.

21. The method of claim 20, wherein:

the evaluation signal is a substantially linear current ramp in a range including the threshold current;

the first response and the second response are sensed before the threshold current is reached; and

the third response is sensed after the threshold current is reached.

22. The method of claim 20, wherein:

the evaluation signal comprises three or more current levels, wherein at least one of the three or more current levels is above the threshold current;

each of the three or more responses are sensed at sample points while a corresponding one of the three or more current levels is being applied to the STT memory cell;

the first response and the second response are sensed at current levels below the threshold current; and

the third response is sensed a current level above the threshold current.

23. An apparatus, comprising:

an array of resistance variable memory cells; and

a controller coupled to the array and configured to determine a data state of a memory cell in the array of resistance variable memory cells by;

applying an evaluation signal to the memory cell, the evaluation signal including a current that goes above a threshold current sufficient to cause the memory cell to switch from a first resistance to a second resistance;

sensing a first response from the memory cell responsive to the evaluation signal at a first sample point;

sensing a second response from the memory cell responsive to the evaluation signal at a second sample point;

sensing a third response from the memory cell responsive to the evaluation signal at a third sample point;

determining a first delta between the first response and the second response;

determining a second delta between the second response and the third response; and

determining whether the memory cell changes from the first resistance to the second resistance during application of the evaluation signal responsive to a difference between the first delta and the second delta.

24. The apparatus of claim 23, wherein:

the memory cell is a Spin Torque Transfer (STT) memory cell with a parallel state and an anti-parallel state;

the first resistance is at one of the anti-parallel state and the parallel state of the STT memory cell; and

the second resistance is at the other one of the anti-parallel state and the parallel state of the STT memory cell.

25. The apparatus of claim 23, wherein the controller is further configured to:

determine that the memory cell was at the first resistance prior to applying the evaluation signal if the memory cell changes; and

determine that the memory cell was at the second resistance prior to applying the evaluation signal if the memory cell does not change.

26. The apparatus of claim 25, wherein:

the memory cell is a Spin Torque Transfer (STT) memory cell with a parallel state and an anti-parallel state;

the first resistance is at one of the anti-parallel state and the parallel state of the STT memory cell; and

the second resistance is at the other one of the anti-parallel state and the parallel state of the STT memory cell.

27. The apparatus of claim 23, wherein the controller is further configured to apply the evaluation signal as a signal selected from the group consisting of a substantially linear current ramp and stepped current levels.