Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules

• US 9,019,779 B2
• Filed: 10/04/2013
• Issued: 04/28/2015
• Est. Priority Date: 05/08/2003
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lee, Terry R., Jeddeloh, Joseph
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US14/046,756
• Publication Number:
  US 20140029325A1
• Time in Patent Office: 571 Days
• Field of Search: 365/189.04, 365/189.03, 365/189.02, 365/189.05, 365/230.03, 365/230.06
• US Class Current: 365/189.03
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/09972 Partitioned, e.g. portions of a PCB dedicated to different functions; Boundary lines therefore; Portions of a PCB being processed separately or differently
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time. In an alternate embodiment, the printed circuit board includes a driver sector electrically isolated from the other sectors and having a multi-layer structure, the driver being attached to the driver sector.

Claims

1. An apparatus comprising:

a plurality of memory devices;

a printed circuit board having a plurality of sectors, each sector of the plurality of sectors being electrically isolated from other sectors of the plurality of sectors, wherein each sector of the plurality of sectors has a respective at least one of the plurality of memory devices attached thereto; and

a plurality of drivers attached to the printed circuit board, wherein each driver of the plurality of drivers is coupled to at least one respective memory device of the plurality of memory devices of a respective sector of the plurality of sectors, each driver of the plurality of drivers configured to be coupled to a memory interface, wherein the plurality of memory sectors are simultaneously accessible by the plurality of drivers so that at least two of the plurality of memory sectors may be accessed at one time.

2. The apparatus of claim 1, wherein a sector of the plurality of sectors has a first side and a second side, and wherein a sector of the plurality of sectors has a first memory device of the plurality of memory devices attached to the first side and a second memory device of the plurality of memory devices attached to the second side.

3. The apparatus of claim 1, wherein a sector of the plurality of sectors has more than one respective memory device attached thereto.

4. The apparatus of claim 1, wherein a number of drivers of the plurality of drivers is equal to a number of sectors of the plurality of sectors.

5. The apparatus of claim 1, wherein the printed circuit board includes a connector configured to connect to a motherboard.

6. The apparatus of claim 5, wherein the printed circuit board includes a plurality of reference planes configured to provide signal return paths, and wherein the plurality of reference planes are coupled together at a plane of the motherboard.

7. The apparatus of claim 5, wherein the motherboard includes segmentation that maintains electrical isolation of the plurality of sectors from each other.

8. The apparatus of claim 1, wherein the printed circuit board includes a multi-layer structure.

9. The apparatus of claim 8, wherein the multi-layer structure includes at least one reference layer configured to provide a return path for received signals.

10. The apparatus of claim 8, wherein the multi-layer structure includes a single reference layer configured to provide the return path for received signals.

11. The apparatus of claim 8, wherein the multi-layer structure includes signal layers that do not cross reference with other signal layers.

12. The apparatus of claim 8, wherein the multi-layer structure includes at least one signal layer, at least one reference layer, and at least one power supply layer.

13. An apparatus, comprising:

a plurality of memory ranks, a rank of the plurality of memory ranks including a respective plurality of memory devices, each memory device of the respective plurality of memory devices attached to a different respective sector of a plurality of sectors, wherein the plurality of sectors are electrically isolated from each other; and

a driver configured to be coupled to the plurality of memory devices of a respective rank of the plurality of memory ranks, wherein the sectors of the plurality of sectors that include a memory device of the plurality of memory devices of the respective rank of the plurality of memory ranks are simultaneously accessible by the driver during a memory access operation.

14. The apparatus of claim 13, wherein the plurality of memory ranks includes four memory ranks, and wherein the plurality of memory devices of the respective rank of the plurality of memory ranks includes four memory devices.

15. The apparatus of claim 13, further comprising a printed circuit board comprising the plurality of sectors to which the plurality of memory devices of the respective rank of the plurality of memory ranks are attached.

16. The apparatus of claim 15, wherein a sector of the plurality of sectors includes a memory device from each of the plurality of memory ranks.

17. The apparatus of claim 16, wherein the sector of the plurality of sectors has a first side and a second side, and wherein a first memory device is attached to the first side and a second memory device is attached to the second side.

18. The apparatus of claim 13, further comprising a driver sector that is electrically isolated from the plurality of memory ranks, wherein the driver is coupled to the driver sector.

19. The apparatus of claim 13, wherein each sector of the plurality of sectors is configured to receive respective command and address signal during the memory access operation that are independent of command and address signal received at other sectors of the plurality of sectors.

20. The apparatus of claim 13, wherein each sector of the plurality of sectors comprises respective power, ground, and signal return paths that are that are independent of power, ground, and signal return paths of other sectors of the plurality of sectors.

21. An apparatus, comprising:

a printed circuit board including a first sector and a second sector, wherein the first sector is electrically isolated from the second sector;

a first memory device attached to the first sector;

a second memory device attached to the second sector; and

a driver configured to contemporaneously access the first memory device of the first sector and the second memory device of the second sector responsive to a memory access operation to a rank of memory including the first and second memory devices.

22. The apparatus of claim 21, wherein the driver comprises a buffer configured to receive command and address signals associated with the memory access operation.

23. The apparatus of claim 21, wherein the driver comprises a hub configured to provide command and address signals associated with the memory access operation to the first and second memory devices.

24. The apparatus of claim 21, wherein the driver comprises a memory access device configured to provide command and address signals associated with the memory access operation to the first and second memory devices.

25. A module comprising:

a plurality of electrically isolated memory sectors, wherein each memory sector of the plurality of electrically isolated memory sectors are configured to be accessed independently; and

a plurality of drivers, wherein each of the plurality of drivers is configured to access a respective one of the plurality of electrically isolated memory sectors.

26. The module of claim 25, wherein one or more memory devices of a memory sector of the plurality of electrically isolated memory sectors are configured to be accessed simultaneously.

27. The module of claim 25, wherein a memory sector of the plurality of electrically isolated memory sectors includes a driver of the plurality of drivers, wherein the driver is coupled to a plurality of memory devices.

28. The module of claim 27, wherein the driver includes a memory access device.

29. The module of claim 27, wherein the driver includes a processor.

30. The module of claim 27, wherein the driver includes a buffer.

31. The module of claim 27, wherein the driver is configured to convert and transmit signals from processing to memory devices included in the memory sectors.

32. The module of claim 27, wherein the driver is configured to convert and transmit signals from the plurality of memory devices to processing, wherein the plurality of memory devices are included in the memory sector.

33. The module of claim 27, wherein the driver is configured to at least one of encode data signals or decode data signals.

34. The module of claim 27, wherein the driver is configured to at least one of multiplex data signals or de-multiplex data signals.

35. The module of claim 25, wherein each memory sector of the plurality of memory sectors includes a respective driver of the plurality of drivers.

36. The module of claim 25, wherein the plurality of memory sectors are configured to be accessed simultaneously.

37. A module comprising:

a plurality of electrically isolated memory sectors, wherein each memory sector of the plurality of electrically isolated memory sectors are configured to be accessed simultaneously; and

a driver configured to access at least one of the plurality of electrically isolated memory sectors.

38. The module of claim 37, wherein the plurality of memory sectors are configured to be accessed independently.

39. The module of claim 37, wherein a memory sector of the plurality of electrically isolated memory sectors includes the driver, wherein the driver is coupled to a plurality of memory devices.

40. The module of claim 39, wherein the driver includes at least one of a memory access device, a processor, or a buffer.

41. The module of claim 39, wherein the plurality of memory devices are included in the memory sector, wherein the driver is configured to convert and transmit signals from processing to the plurality of memory devices included in the at least one memory sector and to convert and transmit signals from the plurality of memory devices to processing.

42. The module of claim 39, wherein the driver is adapted for encoding data signals.

43. The module of claim 39, wherein the driver is adapted for decoding data signals.

44. The module of claim 39, wherein the driver is adapted for multiplexing data signals.

45. The module of claim 39, wherein the driver is adapted for de-multiplexing data signals.

46. The module of claim 37, wherein each memory sector of the plurality of memory sectors includes a respective driver of the plurality of drivers, wherein the driver is included in the plurality of drivers.

47. The module of claim 37, wherein the plurality of memory sectors may be accessed simultaneously.