Transceiver with single coefficient based equalizer taps

• US 9,020,025 B1
• Filed: 06/10/2014
• Issued: 04/28/2015
• Est. Priority Date: 08/24/2000
• Status: Expired due to Fees

• Current Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: He, Runsheng
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US14/300,828
• Time in Patent Office: 322 Days
• Field of Search: 375/232, 375/233, 375/254, 375/346, 375/348, 375/350, 708/322, 708/323
• US Class Current: 375/233
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/0307 using blind adaptation

Abstract

A transceiver including an equalizer and a control circuit. The equalizer receives an input signal and first coefficients. The equalizer includes taps that, based on the first coefficients, filter the input signal to generate an output signal. The taps include a precursor tap, a unity tap and postcursor taps. The control circuit selects the first coefficients such that a sum of the first coefficients is equal to a predetermined value. The first coefficients include a precursor coefficient, a second coefficient, and post cursor coefficients corresponding respectively to the precursor tap, the unity tap, and the postcursor taps. The control circuit: maintains the second coefficient at a fixed value; based on the second coefficient, selects the precursor coefficient and the postcursor coefficients; and while maintaining the second coefficient at the fixed value and while the equalizer is receiving the input signal, adjusts the precursor coefficient or one of the postcursor coefficients.

Claims

1. A transceiver comprising:

an equalizer configured to receive an input signal and a plurality of coefficients, wherein the equalizer comprises a plurality of taps, wherein the plurality of taps are configured to, based on the plurality of coefficients, filter the input signal to generate an output signal, and wherein the plurality of taps comprise at least one precursor tap, a unity tap and postcursor taps; and

a control circuit configured to select the plurality of coefficients such that a sum of the plurality of coefficients is equal to a predetermined value, wherein the plurality of coefficients comprise (i) a first coefficient corresponding to the at least one precursor tap, (ii) a second coefficient corresponding to the unity tap, and (iii) postcursor coefficients corresponding to the postcursor taps, and

wherein the control circuit is further configured to (i) maintain the second coefficient at a fixed value, (ii) based on the second coefficient, select the first coefficient and the postcursor coefficients, and (iii) while maintaining the second coefficient at the fixed value and while the equalizer is receiving the input signal, adjust the first coefficient or one of the postcursor coefficients.

2. The transceiver of claim 1, wherein:

the at least one precursor tap is configured to, based on the first coefficient, filter the input signal to generate a first filtered signal;

the unity tap is configured to, based on the second coefficient, filter the first filtered signal to generate a second filtered signal; and

the postcursor taps are configured to, based on the postcursor coefficients, filter the second filtered signal to generate the output signal.

3. The transceiver of claim 1, wherein:

the plurality of taps comprise precursor taps;

the precursor taps comprise the at least one precursor tap;

the plurality of coefficients comprise precursor coefficients;

the precursor coefficients comprise the first coefficient; and

the precursor taps filter the input signal based on the precursor coefficients.

4. The transceiver of claim 1, wherein:

the equalizer further comprises a plurality of delay elements;

the plurality of delay elements are configured to generate a plurality of delayed versions of the input signal;

the plurality of delayed versions of the input signal comprise a first delayed version, a second delayed version and a second plurality of delayed versions;

the at least one precursor tap is configured to, based on the first delayed version, filter the input signal to generate a first filtered signal;

the unity tap is configured to, based on the second delayed version, filter the first filtered signal to generate a second filtered signal; and

the postcursor taps are configured to, based on the second plurality of delayed versions, filter the second filtered signal to generate the output signal.

5. The transceiver of claim 4, wherein the postcursor taps comprise a plurality of summers configured to generate the output signal by summing (i) the first filtered signal, (ii) the second filtered signal, and (iii) results of multiplying the postcursor coefficients by the second plurality of delayed versions.

6. The transceiver of claim 4, wherein:

the at least one precursor tap is further configured to filter precursor inter-symbol interference in the input signal to generate the first filtered signal; and

the postcursor taps are further configured to filter postcursor inter-symbol interference in the second filtered signal to generate the output signal.

7. The transceiver of claim 1, wherein the control circuit is further configured to, based on least mean square algorithm, maintain the second coefficient at the fixed value while adjusting the first coefficient or the one of the postcursor coefficients.

8. The transceiver of claim 1, further comprising a plurality of least mean square devices configured to adjust the first coefficient and the postcursor coefficients,

wherein the control circuit is configured to maintain the second coefficient at the fixed value while the plurality of least mean square devices adjust the first coefficient and the postcursor coefficients.

9. The transceiver of claim 1, further comprising an error generator configured to generate an error signal based on the output signal,

wherein the control circuit is further configured to, based on the error signal, adjust the first coefficient and the postcursor coefficients.

10. The transceiver of claim 1, further comprising:

a decision feedback equalizer configured to (i) receive the output signal, and (ii) cancel postcursor inter-symbol interference from the output signal; and

an error generator configured to generate an error signal in response to an output of the decision feedback equalizer,

wherein the control circuit is further configured to, based on the error signal, adjust the first coefficient or the postcursor coefficients.

11. The transceiver of claim 10, wherein the decision feedback equalizer comprises:

a decision circuit configured to receive a summation signal;

a feedback filter configured to filter an output of the decision circuit; and

a summer configured to generate the summation signal based on a sum of the output signal and an output of the feedback filter.

12. The transceiver of claim 1, further comprising an error generator configured to (i) detect errors generated during acquisition of the input signal, and (ii) generate an error signal,

wherein the control circuit is further configured to, based on the error signal and an adaptation rate, adaptively adjust the first coefficient or the postcursor coefficients.

13. A method of filtering an input signal via an equalizer, wherein the equalizer comprises a plurality of taps, and wherein the plurality of taps comprise at least one precursor tap, a unity tap and postcursor taps, the method comprising:

receiving the input signal at the equalizer;

receiving a plurality of coefficients at the plurality of taps;

based on the plurality of coefficients, filtering the input signal to generate an output signal;

selecting the plurality of coefficients such that a sum of the plurality of coefficients is equal to a predetermined value, wherein the plurality of coefficients comprise (i) a first coefficient corresponding to the at least one precursor tap, (ii) a second coefficient corresponding to the unity tap, and (iii) postcursor coefficients corresponding to the postcursor taps;

maintaining the second coefficient at a fixed value;

based on the second coefficient, selecting the first coefficient and the postcursor coefficients; and

while maintaining the second coefficient at the fixed value and while the equalizer is receiving the input signal, adjusting the first coefficient or one of the postcursor coefficients.

14. The method of claim 13, further comprising:

based on the first coefficient, filtering the input signal via the at least one precursor tap to generate a first filtered signal;

based on the second coefficient, filtering the first filtered signal via the unity tap to generate a second filtered signal; and

based on the postcursor coefficients, filtering the second filtered signal via the postcursor taps to generate the output signal.

15. The method of claim 13, further comprising, based on precursor coefficients, filtering the input signal via precursor taps, wherein:

the plurality of taps comprise the precursor taps;

the precursor taps comprise the at least one precursor tap;

the plurality of coefficients comprise the precursor coefficients; and

the precursor coefficients comprise the first coefficient.

16. The method of claim 13, further comprising:

generating a plurality of delayed versions of the input signal, wherein the plurality of delayed versions of the input signal comprise a first delayed version, a second delayed version and a second plurality of delayed versions;

based on the first delayed version, filtering the input signal via the at least one precursor tap to generate a first filtered signal;

based on the second delayed version, filtering the first filtered signal via the unity tap to generate a second filtered signal; and

based on the second plurality of delayed versions, filtering the second filtered signal via the postcursor taps to generate the output signal.

17. The method of claim 16, wherein generating the output signal comprises summing (i) the first filtered signal, (ii) the second filtered signal, and (iii) results of multiplying the postcursor coefficients by the second plurality of delayed versions.

18. The method of claim 16, further comprising:

via the at least one precursor tap, filtering precursor inter-symbol interference in the input signal to generate the first filtered signal; and

via the postcursor taps, filtering postcursor inter-symbol interference in the second filtered signal to generate the output signal.

19. The method of claim 13, further comprising:

receiving the output signal at a decision feedback equalizer;

cancelling postcursor inter-symbol interference from the output signal via the decision feedback equalizer;

generating an error signal in response to an output of the decision feedback equalizer; and

based on the error signal, adjusting the first coefficient or the postcursor coefficients.

20. The method of claim 19, further comprising:

receiving a summation signal at a circuit;

filtering an output of the circuit via a feedback filter; and

generating the summation signal based on a sum of the output signal and an output of the feedback filter.