Program suspend/resume for memory

• US 9,021,158 B2
• Filed: 03/15/2013
• Issued: 04/28/2015
• Est. Priority Date: 09/09/2009
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Hyun, Jea Woong, Brinicombe, Mark, Sun, Hairong, Zhong, Hao, Strasser, John, Wood, Robert
• Primary Examiner(s): Alrobaye, Idriss N
• Assistant Examiner(s): MODO, RONALD T
• Application Number:
  US13/834,955
• Publication Number:
  US 20130205085A1
• Time in Patent Office: 774 Days
• US Class Current: 710/48
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 9/485 Task life-cycle, e.g. stopping, restarting, resuming execution G06F9/4881 takes precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

A memory device includes a memory array with a plurality of memory elements. Each memory element is configured to store data. The device includes an input/output (I/O) buffer coupled to the memory array. The I/O buffer is configured to receive data from an I/O interface of a memory device controller and write the data to the memory array. The device includes a memory control manager coupled to the memory array. The memory control manager is configured to pause a program operation to the memory array in response to receiving a pause command. The memory control manager is also configured to resume the program operation in response to receiving a resume command.

Claims

1. An apparatus comprising:

an input/output (I/O) interface configured to couple the apparatus to an I/O buffer coupled to memory elements of a memory device, the I/O buffer residing on the same die as the memory elements;

a program module coupled to the I/O interface, wherein the program module is configured to issue an instruction to the memory device to program user data to the memory device via the I/O buffer; and

a program suspend module coupled to the I/O interface, wherein the program suspend module is configured to;

issue at least one command to the memory device, the at least one command configured to suspend only a specified subset of one or more physical pages of a program operation executing within the memory device in response to receiving a memory read request from an application to perform a read operation on the memory device on which the program operation is being executed; and

issue at least one command to the memory device, the at least one command configured to resume the program operation in response to completing the operation associated with the memory access request.

2. The apparatus of claim 1, wherein the apparatus further comprises a read module coupled to the I/O interface, wherein the read module is configured to receive user data satisfying the read request while the program operation is suspended.

3. The apparatus of claim 1, wherein the program suspend module is further configured to issue a command to the memory device to transfer user data corresponding to the program operation from the I/O buffer to a separate buffer coupled to the I/O buffer in response to receiving the at least one command configured to suspend the program operation.

4. The apparatus of claim 3, wherein the program suspend module is further configured to issue a command to the electronic memory device to transfer the user data corresponding to the program operation from the separate buffer to the I/O buffer in response to completing the operation associated with the memory access request.

5. The apparatus of claim 1, wherein the program suspend module is further configured to:

issue a command to the apparatus to store a pulse count that describes a current programming voltage level corresponding to the program operation; and

issue a command to the apparatus to resume the program operation at the stored pulse count in response to completing the operation associated with the memory access request.

6. The apparatus of claim 1, wherein the program suspend module is further configured to:

issue a command to the apparatus to store a pulse count that describes a current programming voltage level corresponding to the program operation;

calculate a threshold at which to suspend the program operation, wherein the threshold is based on the pulse count; and

issue a command to the memory device controller to suspend the program operation in response to determining that the program operation satisfies the threshold.

7. The apparatus of claim 6, wherein the threshold is further based on a read/write sensitivity of an application requesting access to the memory device.

8. The apparatus of claim 1, wherein the memory access request comprises a program access request with a higher processing priority than the program operation executing within the memory device.

9. A memory device comprising:

a memory array with a plurality of memory elements, wherein each memory element is configured to store data;

an input/output (I/O) buffer coupled to the memory array; and

a cache buffer coupled to the I/O buffer;

a memory control manager coupled to the memory array, wherein the memory control manager is configured to;

pause only a specified subset of one or more physical pages of a program operation to the memory array in response to receiving a pause command;

transfer the data corresponding to the program operation from the cache buffer to the I/O buffer in response to receiving the resume command; and

resume the program operation in response to receiving a resume command.

10. The device of claim 9, wherein the cache buffer is configured to receive and store data from the I/O buffer, wherein the memory control manager is configured to transfer data corresponding to the program operation from the I/O buffer to the cache buffer in response to receiving the pause command.

11. The device of claim 9, further comprising a read buffer coupled to the memory array, wherein the read buffer is configured to:

receive data from the memory array corresponding to a read access request to the memory array while the program operation is paused; and

send the data corresponding to the read access request to an I/O interface.

12. The device of claim 11, wherein the memory control manager is further configured to:

perform a plurality of operations while the program operation is paused, wherein the plurality of operations correspond to a plurality of memory access requests queued behind the program operation.

13. The device of claim 11, further comprising a first sense amplifier and a second sense amplifier coupled to the memory array, wherein the first sense amplifier is further coupled to the read buffer and the second sense amplifier is further coupled to the I/O buffer.

14. The device of claim 9, wherein the memory control manager is further configured to:

store a pulse count that describes a current programming voltage level corresponding to the program operation; and

resume the program operation at the stored pulse count in response to receiving a resume command.

15. The device of claim 9, wherein the memory control manager is further configured to:

store a pulse count that describes a current programming voltage level corresponding to the program operation;

calculate a threshold at which to pause the program operation, wherein the threshold is based on the pulse count; and

pause the program operation in response to determining that the program operation satisfies the threshold.

16. The device of claim 15, wherein the threshold is further based on a read/write sensitivity of an application requesting access to the memory array.

17. The device of claim 15, wherein the threshold is further based on a specified page type of the program operation.

18. A method comprising:

performing a portion of a program operation comprising receiving data from an input/output (I/O) buffer of a memory device and initiating writing the data to memory elements of a memory array, the I/O buffer residing on the same die as the memory elements;

receiving a memory access request at the memory device;

suspending the program operation in response to the program operation satisfying a suspend threshold based on a specified page type for the program operation;

transferring data corresponding to the program operation from the I/O buffer to a cache buffer coupled to the I/O buffer; and

performing an operation for the memory access request.

19. The method of claim 18, wherein the I/O buffer is coupled to the memory array and is configured to store buffered data accessible to the I/O interface.

20. The method of claim 18, wherein the memory access request comprises a read request, wherein the method further comprises:

reading data corresponding to the read request from the memory array to a read buffer coupled to the memory array while the program operation is suspended, wherein the read buffer is separate from the I/O buffer.

21. The method of claim 18, further comprising:

storing a pulse count that describes a current programming voltage level corresponding to the program operation; and

resuming the program operation at the stored pulse count in response to receiving a resume command.

22. The method of claim 18, further comprising:

storing a pulse count that describes a current programming voltage level corresponding to the program operation;

determining a threshold at which to suspend the program operation, wherein the threshold is based on the pulse count; and

suspending the program operation in response to determining that the program operation meets the threshold.

23. The method of claim 18, further comprising suspending only a specified page of the program operation.

24. A system comprising:

means for writing data to a memory device, wherein the memory device comprises an I/O buffer in communication with a memory array with a plurality of memory elements, wherein each memory element is configured to store data and the I/O buffer resides on the same die as the memory elements;

a cache buffer coupled to and located on the same die as the I/O buffer;

means for suspending only a specified subset of one or more pages of a program operation to the memory array in response to receiving a memory access request to the memory device; and

means for resuming the program operation in response to completing an operation associated with the memory access request.