Memory system

• US 9,021,190 B2
• Filed: 01/23/2014
• Issued: 04/28/2015
• Est. Priority Date: 03/01/2008
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yano, Junji, Matsuzaki, Hidenori, Hatsuda, Kosuke
• Primary Examiner(s): DOAN, DUC T
• Application Number:
  US14/162,444
• Publication Number:
  US 20140136772A1
• Time in Patent Office: 460 Days
• Field of Search: None
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7207 management of metadata or control data

Abstract

According to one embodiment, a memory system includes a nonvolatile semiconductor memory include a first area, and a second area smaller than the first area; and a controller configured to control data stored in the nonvolatile semiconductor memory, wherein the nonvolatile semiconductor memory is configured to store a first data accessible by a host command and to a second data inaccessible by the host command, and when receiving the host command, the controller writes the second data of the first area within the second area and initializes a first address information related the first data.

Claims

1. A memory system comprising:

a nonvolatile semiconductor memory including an accessible area being configured to be accessed by an external command, and an inaccessible area being configured not to be accessed by the external command, the external command instructing an erasing processing; and

a controller configured to control data stored in the nonvolatile semiconductor memory, wherein

in response to the controller receiving the external command from a host apparatus, the controller compresses data in the inaccessible area and initializes a management information related to the accessible area.

2. A memory system comprising:

a nonvolatile semiconductor memory; and

a controller configured to control data stored in the nonvolatile semiconductor memory, wherein

the nonvolatile semiconductor memory is configured to store a first data accessible by an external command, and the nonvolatile semiconductor memory is configured to store a second data inaccessible by the external command that instructs an erasing processing, and

when receiving the external command from a host apparatus, the controller compresses the second data and initializes a management information related to the first data.

3. The memory system according to claim 2, further comprising a volatile semiconductor memory in communication with the nonvolatile semiconductor memory, wherein

the controller is configured to read out at least one part of the management information into the volatile semiconductor memory and to update the management information stored in the volatile semiconductor memory, and

when receiving the external command from the host apparatus, the controller initializes the management information stored in the volatile semiconductor memory and writes the initialized management information in the nonvolatile semiconductor memory.

4. The memory system according to claim 3, wherein the nonvolatile semiconductor memory is configured to store a plurality of management tables,

the plurality of management tables include a first management table that records management information including storage positions of data stored in the volatile semiconductor memory and a second management table that records management information including storage positions of data stored in the nonvolatile semiconductor memory, and

when receiving the external command from the host apparatus, the controller initializes the second management table stored in the volatile semiconductor memory and writes the initialized second management table in the nonvolatile semiconductor memory.

5. The memory system according to claim 4, wherein the controller initializes, when receiving the external command from the host apparatus, a section corresponding to first logical addresses in the second management table.

6. The memory system according to claim 5, wherein the controller associates SMART (Self-Monitoring, Analysis and Reporting Technology) information with second logical addresses.

7. The memory system according to claim 3, wherein the volatile semiconductor memory is a DRAM.

8. The memory system according to claim 2, wherein the nonvolatile semiconductor memory is a NAND flash memory.

9. The memory system according to claim 2, wherein when receiving the external command from the host apparatus, the controller erases data associated with first logical addresses in the nonvolatile semiconductor memory.

10. The memory system according to claim 2, wherein the controller determines whether it is necessary to collect data associated with second logical addresses.

11. A memory system comprising:

a nonvolatile semiconductor memory including a first area being configured to be accessed by an external command, and a second area being configured not to be accessed by the external command, the external command instructing an erasing processing; and

a controller configured to compress a data in the second area on the basis of the external command received from a host apparatus and initialize a management information related to the first area.