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Storage system and method for controlling memory in storage system

  • US 9,021,214 B2
  • Filed: 12/14/2011
  • Issued: 04/28/2015
  • Est. Priority Date: 12/14/2011
  • Status: Expired due to Fees
First Claim
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1. A storage system comprising:

  • a first controller having a first processor and a first memory; and

    a second controller having a second processor and a second memory,wherein each of the first and the second memories includes a shared memory storing control information,wherein the first and second controllers are coupled to each other;

    wherein the storage system is configured to have master side information managing a master type of the control information,wherein the first processor is configured to;

    determine whether the control information is double master information or single master information on a basis of the master side information;

    in a case that the control information is the double master information, lock the shared memories in the first and second memories, perform an update process of the control information in the shared memories of the first and second memories, and release the lock of the shared memories in the first and second memories after the update process, the second processor being configured not to perform other update process of the control information in the shared memories of the first and second memories when the shared memories are locked; and

    in a case that the control information is the single master information, perform the update process of the control information without locking the shared memories in the first and second memories,wherein in a case that the control information is the double master information, the control information in the shared memories of the first and second memories is capable of being read from both the first and second processors, andwherein in a case that the control information is the single master information, the control information in only one of the first and second memories is capable of being read from both the first and second processors.

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