Systems and methods for adaptively selecting among different error correction coding schemes in a flash drive

• US 9,021,337 B1
• Filed: 05/22/2012
• Issued: 04/28/2015
• Est. Priority Date: 05/22/2012
• Status: Active Grant

• Current Assignee: Polaris PowerLED Technologies, LLC (Microchip Technology Incorporated)
• Original Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Inventors: Northcott, Philip L.
• Primary Examiner(s): Blair, April Y
• Assistant Examiner(s): GANDHI, DIPAKKUMAR B
• Application Number:
  US13/477,629
• Time in Patent Office: 1,071 Days
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD

Abstract

Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application.

Claims

1. A method of managing one or more gears, wherein different gears correspond to different error correction code (ECC) schemes, the method comprising:

receiving a request for user data stored in flash memory devices, wherein the user data can be in stored in a scrambled from or in an unscrambled form;

retrieving one or more codewords containing the requested user data from a region of the flash memory devices, wherein the region is associated with a first gear;

correcting the one or more codewords to detect and correct errors with the first gear;

deciding whether or not to select a different gear for the region or retiring the region based on at least one of an analysis of an approximate raw bit error rate (RBER) of the region or a number of decoding iterations used to correct the requested user data, wherein the different gear has greater error correction capacity than the first gear; and

after erasure of blocks associated with the region;

when it is decided not to select the different gear, associating the region with a first list of available regions, wherein the first list is associated with the first gear; and

when it is decided to select the different gear, associating the region with a different list of available regions, wherein the different list is associated with the different gear;

wherein at least correcting and deciding are performed by an integrated circuit.

2. The method of claim 1, wherein the region is distributed among a plurality of distinct memory devices, wherein each codeword is distributed among the corresponding memory devices of the region.

3. The method of claim 1, further comprising setting an indication to change the gear associated with the region if it is decided to select the different gear, and leaving the indication unchanged if it is decided not to select the different gear.

4. The method of claim 1, wherein the different gear is selected from a plurality of gears, the plurality of gears varying in data payload size and in corrective capability, wherein the different gear has the next largest amount of data payload size among the plurality of gears.

5. The method of claim 4, wherein there are 3 gears in the plurality of gears.

6. The method of claim 1, wherein the different gear comprises a decrease in a code rate as compared to the first gear.

7. The method of claim 1, wherein a different set of one or more ECC parameters comprises a change in a type of ECC code as compared to a first set.

8. The method of claim 1, wherein the region corresponds to a page stripe or to a page grid.

9. The method of claim 1, wherein deciding whether or not to select a different gear for the region or retiring the region is based on the RBER of the region.

10. The method of claim 1, wherein deciding whether or not to select a different gear for the region or retiring the region is based on the number of decoding iterations used to correct the requested user data.

11. A method of managing one or more gears, wherein different gears correspond to different error correction code (ECC) schemes, the method comprising:

receiving a request for user data stored in flash memory devices, wherein the user data can be in stored in a scrambled from or in an unscrambled form;

retrieving one or more codewords containing the requested user data from a region of the flash memory devices, wherein the region is associated with a first gear;

correcting the one or more codewords to detect and correct errors with the first gear; and

deciding whether or not to select a different gear for the region or retiring the region based on at least one of an analysis of an approximate raw bit error rate (RBER) of the region or a number of decoding iterations used to correct the requested user data, wherein the different gear has greater error correction capacity than the first gear;

wherein the analysis of the approximate RBER further comprises comparing the approximate RBER against one or more threshold limits, wherein at least one of the approximate RBER or the one or more threshold limits is modified by a safety factor, wherein the safety factor accounts for uncertainty in estimating future RBER;

wherein at least correcting and deciding are performed by an integrated circuit.

12. The method of claim 11, further comprising determining at least an approximate raw bit error rate (RBER) based on a number of corrected bits encountered during decoding of the one or more codewords.

13. The method of claim 11, wherein error correction according to a gear is performed in an iterative fashion using multiple error correction codes having multiple dimensions, further comprising estimating the approximate RBER by summing a number of bits flipped during the iterative correction.

14. An apparatus comprising:

a first circuit configured to;

receive a request for user data stored in flash memory devices, wherein the user data can be in stored in a scrambled from or in an unscrambled form; and

retrieve one or more codewords containing the requested user data from a region of the flash memory devices, wherein the region is associated with a first gear, wherein different gears correspond to different error correction code (ECC) schemes; and

a second circuit configured to correct the one or more codewords to detect and correct errors with the first gear;

wherein the first circuit is configured to decide whether or not to select a different gear for the region or retire the region based on at least one of an analysis of an approximate raw bit error rate (RBER) of the region or a number of decoding iterations used to correct the requested user data, wherein the different gear has greater error correction capacity than the first gear, wherein, after erasure of blocks associated with the region, the first circuit is configured to;

associate the region with a first list of available regions when it is decided not to select the different gear, wherein the first list is associated with the first gear; and

associate the region with a different list of available regions when it is decided to select the different gear, wherein the different list is associated with the different gear.

15. The apparatus of claim 14, wherein the region is distributed among a plurality of distinct memory devices, wherein each codeword is distributed among the corresponding memory devices of the region.

16. The apparatus of claim 14, wherein the first circuit is further configured to set an indication to change the gear associated with the region if it is decided to select the different gear, and to leave the indication unchanged if it is decided not to select the different gear.

17. The apparatus of claim 14, wherein the different gear is selected from a plurality of gears, the plurality of gears varying in data payload size and in corrective capability, wherein the different gear has the next largest amount of data payload size among the plurality of gears.

18. The apparatus of claim 17, wherein there are 3 gears in the plurality of gears.

19. The apparatus of claim 14, wherein the different gear comprises a decrease in a code rate as compared to the first gear.

20. The apparatus of claim 14, wherein a different set of one or more ECC parameters comprises a change in a type of ECC code as compared to a first set.

21. The apparatus of claim 14, wherein the region corresponds to a page stripe or to a page grid.

22. The apparatus of claim 14, wherein the first circuit is configured to decide whether or not to select a different gear for the region or retire the region based on the analysis of the RBER of the region.

23. The apparatus of claim 14, wherein the first circuit is configured to decide whether or not to select a different gear for the region or retire the region based on the number of decoding iterations used to correct the requested user data.

24. An apparatus comprising:

a first circuit configured to;

receive a request for user data stored in flash memory devices, wherein the user data can be in stored in a scrambled from or in an unscrambled form; and

retrieve one or more codewords containing the requested user data from a region of the flash memory devices, wherein the region is associated with a first gear, wherein different gears correspond to different error correction code (ECC) schemes; and

a second circuit configured to correct the one or more codewords to detect and correct errors with the first gear;

wherein the first circuit is configured to decide whether or not to select a different gear for the region or retire the region based on at least one of an analysis of an approximate raw bit error rate (RBER) of the region or a number of decoding iterations used to correct the requested user data, wherein the different gear has greater error correction capacity than the first gear, wherein for analysis of the approximate RBER, the first circuit is further configured to compare the approximate RBER against one or more threshold limits, wherein at least one of the approximate RBER or the one or more threshold limits is modified by a safety factor, wherein the safety factor accounts for uncertainty in estimating future RBER.

25. The apparatus of claim 24, wherein the first circuit or the second circuit is further configured to estimate at least an approximate raw bit error rate (RBER) based on a number of corrected bits encountered during decoding of the one or more codewords.

26. The apparatus of claim 24, wherein the second circuit is configured to perform error correction in an iterative fashion with multiple error correction codes having multiple dimensions, wherein the first circuit is further configured to estimate the approximate RBER by summing a number of bits flipped during the iterative correction.

27. An apparatus of managing one or more gears, wherein different gears correspond to different error correction code (ECC) schemes, the apparatus comprising:

a means for receiving a request for user data stored in flash memory devices, wherein the user data can be in stored in a scrambled from or in an unscrambled form;

a means for retrieving one or more codewords containing the requested user data from a region of the flash memory devices, wherein the region is associated with a first gear;

a means for correcting the one or more codewords to detect and correct errors with the first gear; and

a means for deciding whether or not to select a different gear for the region or retiring the region based on at least one of an analysis of an approximate raw bit error rate (RBER) of the region or a number of decoding iterations used to correct the requested user data, wherein the different gear has greater error correction capacity than the first gear, wherein, after erasure of blocks associated with the region, the deciding means is further configured to;

associate the region with a first list of available regions when it is decided not to select the different gear, wherein the first list is associated with the first gear; and

associate the region with a different list of available regions when it is decided to select the different gear, wherein the different list is associated with the different gear.

28. The apparatus of claim 27, wherein the region is distributed among a plurality of distinct memory devices, wherein each codeword is distributed among the corresponding memory devices of the region.

29. The apparatus of claim 27, wherein the deciding means is further configured to set an indication to change the gear associated with the region if it is decided to select the different gear, and leaving the indication unchanged if it is decided not to select the different gear.

30. The apparatus of claim 27, wherein the different gear is selected from a plurality of gears, the plurality of gears varying in data payload size and in corrective capability, wherein the different gear has the next largest amount of data payload size among the plurality of gears.

31. The apparatus of claim 30, wherein there are 3 gears in the plurality of gears.

32. The apparatus of claim 27, wherein the different gear comprises a decrease in a code rate as compared to the first gear.

33. The apparatus of claim 27, wherein a different set of one or more ECC parameters comprises a change in a type of ECC code as compared to a first set.

34. The apparatus of claim 27, wherein the region corresponds to a page stripe or to a page grid.

35. The apparatus of claim 27, wherein the deciding means is configured to decide whether or not to select a different gear for the region or retiring the region based on the RBER of the region.

36. The apparatus of claim 27, wherein the deciding means is configured to decide whether or not to select a different gear for the region or retiring the region based on the number of decoding iterations used to correct the requested user data.

37. An apparatus of managing one or more gears, wherein different gears correspond to different error correction code (ECC) schemes, the apparatus comprising:

a means for receiving a request for user data stored in flash memory devices, wherein the user data can be in stored in a scrambled from or in an unscrambled form;

a means for retrieving one or more codewords containing the requested user data from a region of the flash memory devices, wherein the region is associated with a first gear;

a means for correcting the one or more codewords to detect and correct errors with the first gear; and

a means for deciding whether or not to select a different gear for the region or retiring the region based on at least one of an analysis of an approximate raw bit error rate RBER of the re ion or a number of decoding iterations used to correct the re-quested user data, wherein the different gear has greater error correction capacity than the first gear, wherein for analysis of the approximate RBER, the deciding means is further configured to compare the approximate RBER against one or more threshold limits, wherein at least one of the approximate RBER or the one or more threshold limits is modified by a safety factor, wherein the safety factor accounts for uncertainty in estimating future RBER.

38. The apparatus of claim 37, further comprising means for determining at least an approximate raw bit error rate (RBER) based on a number of corrected bits encountered during decoding of the one or more codewords.

39. The apparatus of claim 37, wherein the correcting means is configured to perform error correction in an iterative fashion using multiple error correction codes having multiple dimensions, wherein the deciding means is further configured to estimate the approximate RBER by summing a number of bits flipped during the iterative correction.