Electronic system with multi-cycle simulation coverage mechanism and method of operation thereof

• US 9,021,410 B1
• Filed: 02/18/2014
• Issued: 04/28/2015
• Est. Priority Date: 12/10/2013
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Hoidn, Markus J.
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): Alam, Mohammed
• Application Number:
  US14/182,628
• Time in Patent Office: 434 Days
• Field of Search: 716/108
• US Class Current: 716/108
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

An apparatus includes: a storage unit configured to provide a device design; a control unit configured to analyze the device design for a multi-cycle exception, generate a multi-cycle exception profile, and generate a checker based on the multi-cycle exception profile for a test bench for a simulation version of the device design.

Claims

1. An apparatus comprising:

a storage unit configured to provide a device design including a source element and a destination element; and

a control unit configured to;

analyze vectorlessly the device design for a multi-cycle exception,

generate a multi-cycle exception profile including the source element running off a source clock and the destination element running off a destination where the source clock and the destination clock are in different clock domains, and

generate a checker for the source element based on the multi-cycle exception profile for a test bench for a simulation version of the device design.

2. The apparatus as claimed in claim 1 wherein the multi-cycle exception profile includes a multi-cycle clock exception between a source block and a destination block in the device design.

3. The apparatus as claimed in claim 1 wherein the device design comprises a non-high level description language design.

4. The apparatus as claimed in claim 1 wherein the device design comprises a high level description language design.

5. The apparatus as claimed in claim 1 wherein the control unit is further configured to:

analyze the simulation version representing a high level simulation for a high level description language design; and

generate the checker for the test bench for the simulation version also representing the high level simulation for the high level description language design.

6. The apparatus as claimed in claim 1 wherein the simulation version comprises a non-high level description language design.

7. The apparatus as claimed in claim 2 wherein the checker includes a description for a path from the source element in the source block to the destination element in the destination block.

8. The apparatus as claimed in claim 1 wherein the checker includes an operational reset for the device design.

9. The apparatus as claimed in claim 1 wherein the checker includes a notification function that is triggered when a violation of the multi-cycle exception is detected during a simulation of the simulation version.

10. The apparatus as claimed in claim 9 wherein the violation is manifested at an external output of the device design.

11. A method comprising:

analyzing vectorlessly, using a computer having at least one processor, a device design comprising a source element and a destination element for a multi-cycle exception;

generating a multi-cycle exception profile including the source element running off a source clock and the destination element running off a destination clock where the source clock and the destination clock are in different clock domains; and

generating a checker for the source element based on the multi-cycle exception profile for a test bench for a simulation version of the device design.

12. The method as claimed in claim 11 wherein the multi-cycle exception profile includes a multi-cycle clock exception between a source block and a destination block in the device design.

13. The method as claimed in claim 11 wherein the device design comprises a non-high level description language design.

14. The method as claimed in claim 11 wherein the device design comprises a high level description language design.

15. The method as claimed in claim 11 wherein:

analyzing vectorlessly the device design includes analyzing the simulation version representing a high level simulation for a high level description language design; and

generating the checker includes generating the checker for the test bench for the simulation version also representing the high level simulation for the high level description language design.

16. The method as claimed in claim 11 wherein the simulation version comprises a non-high level description language design.

17. The method as claimed in claim 12 wherein the checker includes a description for a path from the source element in the source block to the destination element in the destination block.

18. The method as claimed in claim 11 wherein the checker includes an operational reset for the device design.

19. The method as claimed in claim 11 wherein the checker includes a notification function when a violation of the multi-cycle exception is detected during a simulation of the simulation version.

20. The method as claimed in claim 19 wherein the violation is manifested at an external output of the device design.

21. A non-transitory computer readable medium including instructions for execution, by a computer, the instructions comprising instructions for:

analyzing vectorlessly a device design comprising a source element and a destination element for a multi-cycle exception,

generating a multi-cycle exception profile including the source element running off a source clock and the destination element running off a destination clock where the source clock and the destination dock are in different clock domains, and

generating a checker for the source element based on the multi-cycle exception profile for a test bench for a simulation version of the device design.

22. The medium as claimed in claim 21 wherein the multi-cycle exception profile includes a multi-cycle clock exception between a source block and a destination block in the device design.

23. The medium as claimed in claim 21 wherein the device design comprises a non-high level description language design.

24. The medium as claimed in claim 21 wherein the device design comprises a high level description language design.

25. The medium as claimed in claim 21 wherein:

analyzing vectorlessly the device design includes analyzing the simulation version representing a high level simulation for a high level description language design; and

generating the checker includes generating the checker for the test bench for the simulation version also representing the high level simulation for the high level description language design.

26. The medium as claimed in claim 21 wherein the simulation version comprises a non-high level description language design.

27. The medium as claimed in claim 22 wherein the checker includes a description for a path from the source element in the source block to the destination element in the destination block.

28. The medium as claimed in claim 21 wherein the checker includes an operational reset for the device design.

29. The medium as claimed in claim 21 wherein the checker includes a notification function when a violation of the multi-cycle exception is detected during a simulation of the simulation version.

30. The medium as claimed in claim 29 wherein the violation is manifested at an external output of the device design.