High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture

• US 9,023,698 B2
• Filed: 04/13/2012
• Issued: 05/05/2015
• Est. Priority Date: 10/20/2003
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chen, Huajie, Chidambarrao, Dureseti, Dokumaci, Omer H.
• Primary Examiner(s): Smoot, Stephen W
• Application Number:
  US13/446,609
• Publication Number:
  US 20120196412A1
• Time in Patent Office: 1,117 Days
• Field of Search: 438/230
• US Class Current: 438/230
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.

Claims

1. A method of manufacturing a semiconductor structure, comprising:

forming a pFET stack and an nFET stack on a substrate;

forming first source/drain regions at the substrate adjacent respective opposing sides of the pFET stack;

growing a first layer of material at the first source/drain regions associated with the pFET stack, wherein after the growing, the first layer of material has a lattice structure that matches a lattice structure of a first underlying portion of the substrate to create a compressive state within a pFET channel;

forming second source/drain regions at the substrate adjacent respective opposing sides of the nFET stack, wherein forming the first and second source/drain regions comprises;

forming a first protection layer;

forming a first mask on only a portion of the first protection layer and on the nFET stack, the first mask exposing the pFET stack; and

performing a first etching process using the first mask as an etching mask;

forming a second protection layer;

forming a second mask on only a portion of the second protection layer and on the pFET stack, the second mask exposing the nFET stack; and

performing a second etching process using the second mask as an etching mask; and

growing a second layer of material at the second source/drain regions associated with the nFET stack, wherein after the growing, the second layer of material has a lattice structure that matches a lattice structure of a second underlying portion of the substrate to create a tensile state within an nFET channel.

2. The method of claim 1, wherein:

before the first layer of material at the first source/drain regions associated with the pFET is grown, the material forming the first layer has a lattice constant different than a first base lattice constant of the substrate.

3. The method of claim 1, wherein:

before the second layer of material at the second source/drain regions associated with the nFET is grown, the material forming the second layer has a lattice constant different than a second base lattice constant of the substrate.

4. The method of claim 1, wherein the second layer of material comprises a highly tensile Si:

C film to longitudinally apply tension in the nFET channel.

5. The method of claim 4, wherein the second layer of material is embedded in the substrate in the second source/drain regions.

6. The method of claim 5, wherein:

the second source/drain regions comprise recessed source/drain regions;

performing the second etching process comprises etching the substrate to form the recessed source/drain regions; and

growing the second layer of material comprises growing the Si;

C in the recessed source/drain regions.

7. The method of claim 6, wherein growing the Si:

C comprises epitaxially growing the Si;

C in the recessed source/drain regions to a thickness of about 10 to about 100 nm.

8. The method of claim 6, wherein the Si:

C has a C concentration of greater than 0% to 4% in ratio to Si.

9. The method of claim 1, wherein the first layer of material associated with the pFET stack is a highly compressive SiGe film to longitudinally apply compression in the pFET channel.

10. The method of claim 9, wherein the first layer of material associated with the pFET stack is embedded in the substrate.

11. The method of claim 10, wherein:

the first source/drain regions comprise recessed source/drain regions;

performing the first etching process comprises etching the substrate to form the recessed source/drain regions; and

growing the first layer of material comprises growing the SiGe in the recessed source/drain regions.

12. The method of claim 11, wherein growing the SiGe comprises epitaxially growing the SiGe in the recessed source/drain regions to a thickness of about 10 to about 100 nm.

13. The method of claim 11, wherein growing the SiGe comprises epitaxially growing the SiGe to protrude above a surface of the substrate.

14. The method of claim 1, wherein:

the first layer of material comprises first and second portions, respectively, adjacent first and second ones of the opposing sides of the pFET stack;

the second layer of material comprises first and second portions, respectively, adjacent first and second ones of the opposing sides of the nFET stack;

the pFET channel comprises a pFET channel region that is between the first and second portions of the first layer of material; and

the nFET channel comprises an nFET channel region that is between the first and second portions of the second layer of material.

15. The method of claim 1, wherein forming the second mask comprises forming the second mask on the first layer of material at the first source/drain regions, and wherein forming the second source/drain regions comprises forming the second source/drain regions with the second mask on the first layer of material at the first source/drain regions.

16. The method of claim 1, wherein forming the second protection layer comprises:

forming the second protection layer on the nFET stack, the pFET stack, and the first source/drain regions, after performing the first etching process using the first mask, and before forming the second mask and the second source/drain regions.

17. The method of claim 1, further comprising forming an isolation region in the substrate, wherein forming the first mask comprises forming the first mask on only a first portion of the isolation region, and wherein forming the second mask comprises forming the second mask on only a second portion of the isolation region.

18. The method of claim 17,

wherein forming the first protection layer comprises forming the first protection layer on the isolation region before forming the first mask, and

wherein forming the second protection layer comprises forming the second protection layer on the isolation region before forming the second mask.

19. A method of manufacturing a semiconductor structure, the method comprising:

forming a pFET stack and an nFET stack on a substrate;

forming first source/drain regions at the substrate adjacent respective opposing sides of the pFET stack, wherein forming the first source/drain regions comprises;

forming a first protection layer;

forming a first mask on the nFET stack and partially on the first protection layer; and

performing a first etching process using the first mask as an etching mask;

growing a first layer of material at the first source/drain regions associated with the pFET stack, wherein the first layer of material provides a compressive state in a pFET channel associated with the pFET stack;

forming second source/drain regions at the substrate adjacent respective opposing sides of the nFET stack, wherein forming the second source/drain regions comprises;

forming a second protection layer;

forming a second mask on the pFET stack and partially on the second protection layer; and

performing a second etching process using the second mask as an etching mask; and

growing a second layer of material at the second source/drain regions associated with the nFET stack, wherein the second layer of material provides a tensile state in an nFET channel associated with the nFET stack.

20. The method of claim 19,

wherein an isolation region is in the substrate between the pFET stack and the nFET stack,

wherein forming the first mask comprises forming the first mask on the nFET stack and partially on the first protection layer to expose a portion of the first protection layer on the isolation region, and

wherein forming the second mask comprises forming the second mask on the pFET stack and partially on the second protection layer to expose a portion of the second protection layer on the isolation region.