Method of forming semiconductor device

• US 9,023,708 B2
• Filed: 04/19/2013
• Issued: 05/05/2015
• Est. Priority Date: 04/19/2013
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chen, Li-Chiang, Liao, Jiunn-Hsiung, Chen, Hsuan-Hsu, Chang, Feng-Yi, Chen, Chieh-Te, Tsai, Shang-Yuan, Hsu, Ching-Pin
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): JUNGE, BRYAN R.
• Application Number:
  US13/866,456
• Publication Number:
  US 20140315365A1
• Time in Patent Office: 746 Days
• US Class Current: 438/299
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A method of forming a semiconductor device is provided. At least one gate structure including a dummy gate is formed on a substrate. A contact etch stop layer and a dielectric layer are formed to cover the gate structure. A portion of the contact etch stop layer and a portion of the dielectric layer are removed to expose the top of the gate structure. A dry etching process is performed to remove a portion of the dummy gate of the gate structure. A hydrogenation treatment is performed to the surface of the remaining dummy gate. A wet etching process is performed to remove the remaining dummy gate and thereby form a gate trench.

Claims

1. A method of forming a semiconductor device, comprising:

forming at least one gate structure on a substrate, wherein the gate structure comprises a dummy gate;

forming a contact etch stop layer and a dielectric layer to cover the gate structure;

removing a portion of the contact etch stop layer and a portion of the dielectric layer to expose a top of the gate structure;

performing a dry etching process to remove a portion of the dummy gate of the gate structure;

performing a hydrogenation treatment to a surface of the remaining dummy gate, wherein a gas is used in the hydrogenation treatment and the hydrogenation treatment reduces an amount of a crystallographic plane {111} in the dummy gate; and

performing a wet etching process to remove the remaining dummy gate and thereby form a gate trench.

2. The method of claim 1, wherein a gas used in the hydrogenation treatment comprises H_z, H₂N₂, He or a combination thereof.

3. The method of claim 1, wherein a gas used in the dry etching process comprises Cl₂, HBr, NH₃ or a combination thereof.

4. The method of claim 1, wherein an ethant used in the wet etching process comprises tetramethyl ammonium hydroxide (TMAH).

5. The method of claim 1, wherein the dummy gate comprises pure amorphous silicon or a combination of amorphous silicon and crystalline silicon.

6. The method of claim 1, wherein a method of forming the dummy gate comprises:

forming an amorphous silicon layer; and

performing an annealing process to the amorphous silicon layer so as to partially transform the amorphous silicon layer into a polysilicon layer.

7. The method of claim 1, wherein the gate structure comprises an interfacial layer and the dummy gate.

8. The method of claim 7, wherein the interfacial layer comprises silicon oxide, silicon oxynitride, a high-k material with a dielectric constant greater than 4, or a combination thereof.

9. The method of claim 7, wherein the gate structure further comprises:

a spacer, disposed on the substrate on a sidewall of the dummy gate; and

two source/drain regions, disposed in the substrate beside the dummy gate, and

wherein the two source/drain regions comprise doped regions, SiGe, SiC, SiP or a combination thereof.

10. A method of forming a semiconductor device, comprising:

forming at least one gate structure on a substrate, wherein the gate structure comprises a dummy gate;

forming a contact etch stop layer and a dielectric layer to cover the gate structure;

removing a portion of the contact etch stop layer and a portion of the dielectric layer to expose a top of the gate structure;

performing a dry etching process to remove a portion of the dummy gate of the gate structure;

performing a hydrogenation treatment to a surface of the remaining dummy gate, so as to form a protection layer on a surface of the remaining dummy gate, wherein a gas is used in the hydrogenation treatment and an amount of a crystallographic plane {111} of the protection layer is lower than an amount of a crystallographic plane {111} of the dummy gate; and

performing a wet etching process to remove the protection layer and the remaining dummy gate and thereby form a gate trench.

11. The method of claim 10, wherein the protection layer comprises Si—

H bonds.

12. The method of claim 10, wherein a gas used in the dry etching process comprises Cl₂, HBr, NH₃ or a combination thereof.

13. The method of claim 10, wherein an ethant used in the wet etching process comprises tetramethyl ammonium hydroxide (TMAH).

14. The method of claim 10, wherein the dummy gate comprises pure amorphous silicon or a combination of amorphous silicon and crystalline silicon.

15. The method of claim 10, wherein a method of forming the dummy gate comprises:

forming an amorphous silicon layer; and

performing an annealing process to the amorphous silicon layer so as to partially transform the amorphous silicon layer into a polysilicon layer.

16. The method of claim 10, wherein the gate structure comprises an interfacial layer and the dummy gate.

17. The method of claim 16, wherein the interfacial layer comprises silicon oxide, silicon oxynitride, a high-k material with a dielectric constant greater than 4, or a combination thereof.

18. The method of claim 16, wherein the gate structure further comprises:

a spacer, disposed on the substrate on a sidewall of the dummy gate; and

two source/drain regions, disposed in the substrate beside the dummy gate, and

wherein the two source/drain regions comprise doped regions, SiGe, SiC, SiP or a combination thereof.