High aspect ratio memory hole channel contact formation

• US 9,023,719 B2
• Filed: 03/25/2014
• Issued: 05/05/2015
• Est. Priority Date: 09/17/2013
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Pachamuthu, Jayavel, Alsmeier, Johann, Makala, Raghuveer S., Lee, Yao-Sheng
• Primary Examiner(s): Smoot, Stephen W
• Assistant Examiner(s): Chin, Edward
• Application Number:
  US14/225,116
• Publication Number:
  US 20150079765A1
• Time in Patent Office: 406 Days
• US Class Current: 438/492
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A method of fabricating a semiconductor device, such as a three-dimensional monolithic NAND memory string, includes etching a select gate electrode over a first gate insulating layer over a substrate to form an opening, forming a second gate insulating layer over the sidewalls of the opening, forming a sacrificial spacer layer over the second gate insulating layer on the sidewalls of the opening, and etching the first gate insulating layer over the bottom surface of the opening to expose the substrate, removing the sacrificial spacer layer to expose the second gate insulating layer over the sidewalls of the opening, and forming a protrusion comprising a semiconductor material within the opening and contacting the substrate, wherein the second gate insulating layer is located between the select gate electrode and first and second side surfaces of the protrusion.

Claims

1. A method of fabricating a memory device, comprising:

forming a first gate insulating layer over a major surface of a semiconductor substrate;

forming a select gate electrode over the first gate insulating layer;

etching the select gate electrode to the first gate insulating layer through a mask to form an opening having sidewalls and a bottom surface, wherein the select gate electrode forms at least a portion of the sidewalls and the first gate insulating layer forms the bottom surface;

forming a second gate insulating layer on the sidewalls of the opening;

forming a sacrificial spacer layer over the second gate insulating layer on at least the sidewalls of the opening;

etching the first gate insulating layer over the bottom surface of the opening to expose the semiconductor substrate while the sacrificial spacer layer protects the second gate insulating layer on the sidewalls of the opening;

removing the sacrificial spacer layer to expose the second gate insulating layer over the sidewalls of the opening; and

forming a protrusion comprising a semiconductor material within the opening and contacting the semiconductor substrate, the protrusion having a top surface substantially parallel to the major surface of the substrate, a first side surface and a second side surface opposite the first side surface and the second gate insulating layer is located between the conductive select gate electrode and the first and second side surfaces of the protrusion.

2. The method of claim 1, wherein removing the sacrificial spacer layer exposes a peripheral region of the second gate insulating layer over the bottom surface of the opening, the peripheral region defining an open region exposing the semiconductor substrate.

3. The method of claim 2, wherein forming the protrusion comprises forming the protrusion over the open region and over the peripheral region on the bottom surface of the opening.

4. The method of claim 1, wherein forming the protrusion comprises epitaxially growing a semiconductor material in the opening using a seed material.

5. The method of claim 4, wherein the semiconductor material comprises epitaxially-gown silicon.

6. The method of claim 1, wherein forming the sacrificial spacer layer comprises forming the sacrificial spacer layer over the second gate insulating layer on the sidewalls and the bottom surface of the opening, and wherein etching the first gate insulating layer comprises etching the sacrificial spacer layer and the first gate insulating layer over the bottom surface of the opening to expose the semiconductor substrate while the sacrificial spacer layer protects the second gate insulating layer from being etched on the sidewalls of the opening.

7. The method of claim 6, wherein the sacrificial spacer layer comprises silicon nitride.

8. The method of claim 7, wherein removing the sacrificial spacer layer comprises wet etching the sacrificial spacer layer.

9. The method of claim 1, wherein forming the sacrificial spacer layer comprises depositing a sacrificial material that preferentially forms on the sidewalls and not on the bottom surface of the opening.

10. The method of claim 1, wherein the sacrificial spacer layer comprises carbon.

11. The method of claim 10, wherein removing the sacrificial spacer layer comprises ashing the sacrificial spacer layer.

12. The method of claim 4, wherein epitaxially growing the semiconductor material in the opening comprises partially filling the opening with the epitaxially-grown semiconductor material and forming the semiconductor material protrusion further comprises depositing a second material layer over the epitaxially-grown semiconductor material to completely fill the opening.

13. The method of claim 12, wherein the second material layer comprises a second semiconductor material.

14. The method of claim 13, wherein the depositing the second semiconductor material comprises depositing polysilicon using plasma enhanced chemical vapor deposition.

15. The method of claim 14, wherein the polysilicon is doped.

16. The method of claim 14, wherein the polysilicon is undoped.

17. The method of claim 12, wherein the second material layer comprises at least one of a metal and a metal nitride.

18. The method of claim 17, wherein the second material layer comprises at least one of tungsten, tungsten nitride, tantalum, titanium, titanium nitride and cobalt.

19. The method of claim 1, wherein forming the protrusion comprises forming the protrusion in the opening that extends above a top of the opening and planarizing the protrusion to define the top surface of the protrusion such that that the protrusion does not extend outside of the opening.

20. The method of claim 1, further comprising:

forming an etch stop layer over the top surface of the protrusion;

forming a stack of alternating layers of a first material and a second material different from the first material over the etch stop layer;

etching the stack through a mask to the etch stop layer to form a memory opening having a first width dimension proximate to the etch stop layer;

etching the etch stop layer to provide a void area between the top surface of the protrusion and a bottom of the memory opening, the void area having a second width dimension that is larger than the first width dimension;

forming at least a portion of a memory film over a sidewall of the memory opening and within the void area over the top surface of the protrusion;

etching the memory film to expose the top surface of the protrusion; and

forming a semiconductor channel in the memory opening such that the semiconductor channel is electrically coupled to the protrusion and the at least a portion of the memory film is located between the semiconductor channel and the sidewall of the memory opening.

21. The method of claim 20, wherein the stack is etched to the etch stop layer using a first etching process and the etch stop layer is etched to provide the void area using a second etching process different than the first etching process, and the etch stop layer comprises a material with a higher etch rate using the second etching process than with the first etching process.

22. The method of claim 21, wherein the etch stop layer comprises a material with a higher etch rate than the stack and the protrusion using the second etching process.

23. The method of claim 21, wherein the first etching process comprises a reactive ion etching process and the second etching process comprises a wet etching process.

24. The method of claim 20, wherein the etch stop layer comprises intrinsic polysilicon.

25. The method of claim 20, wherein the etch stop layer comprises at least one of a nitride and an oxide material.

26. The method of claim 20, wherein the memory film comprises a charge trapping layer or floating gate and a tunnel dielectric, and the tunnel dielectric is located between the charge trapping layer or floating gate and the semiconductor channel.

27. The method of claim 26, wherein the at least one memory film further comprises a blocking dielectric.

28. The method of claim 27, wherein the memory device comprises a three dimensional monolithic NAND string and wherein the second material layers comprise control gate electrodes or sacrificial layers which are replaced with conductive control gate electrodes after forming the semiconductor channel.

29. The method of claim 20, further comprising:

forming a sacrificial semiconductor layer over the at least a portion of the memory film along the sidewall of the memory opening and in the void area over the top surface of the protrusion; and

etching the sacrificial semiconductor layer and the memory film to expose the top surface of the protrusion, wherein the semiconductor channel is formed over the sacrificial semiconductor layer along at least the sidewall of the memory opening.

30. The method of claim 20, wherein etching the memory film to expose the top surface of the protrusion comprises forming a generally cylindrically-shaped opening through the memory film in the void area to expose the top surface of the protrusion, and forming the semiconductor channel comprises forming a generally cylindrically-shaped protruding region of the semiconductor channel within the generally cylindrically-shaped opening such that a bottom surface of the protruding region contacts the top surface of the protrusion.

31. The method of claim 1, wherein forming the select gate electrode over the first gate insulating layer comprises:

forming a layer of semiconductor material over the first gate insulating layer; and

forming at least one of a metal layer and a metal nitride layer over the layer of semiconductor material.

32. The method of claim 31, wherein the layer of semiconductor material comprises polysilicon, and forming at least one of a metal layer and a metal nitride layer comprises forming a metal nitride layer over the polysilicon layer and forming a metal layer over the metal nitride layer.

33. The method of claim 32, wherein the metal nitride layer comprises tungsten nitride and the metal layer comprises tungsten, the method further comprising forming a silicon nitride cap layer over the tungsten layer.

34. The method of claim 17, further comprising forming a metal silicide in an interface region between the semiconductor channel and the protrusion.

35. The method of claim 34, wherein forming the metal silicide comprises reacting the semiconductor channel with a metal or metal nitride region in an upper portion of the protrusion using selective laser annealing.

36. The method of claim 34, wherein the metal silicide comprises at least one of WSi₂, TaSi₂, TiSiN, TiSi₂ and CoSi₂.