Horizontally oriented and vertically stacked memory cells

• US 9,024,283 B2
• Filed: 02/05/2013
• Issued: 05/05/2015
• Est. Priority Date: 06/22/2010
• Status: Active Grant

• Current Assignee: Ovonyx Memory Technology, LLC (Micron Technology, Inc.)
• Original Assignee: Micron Technology, Inc.
• Inventors: Quick, Timothy A., Marsh, Eugene P.
• Primary Examiner(s): Valentine, Jami M
• Application Number:
  US13/759,576
• Publication Number:
  US 20130153853A1
• Time in Patent Office: 819 Days
• Field of Search: 438102-104, 257 2- 5, 257/E29.002
• US Class Current: 257/2
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/026 by physical vapor deposition, e.g. sputtering
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/821 Device geometry
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/841 Electrodes
• CPC Class Codes: H10N 70/881 Switching materials
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels

Abstract

Horizontally oriented and vertically stacked memory cells are described herein. One or more method embodiments include forming a vertical stack having a first insulator material, a first memory cell material on the first insulator material, a second insulator material on the first memory cell material, a second memory cell material on the second insulator material, and a third insulator material on the second memory cell material, forming an electrode adjacent a first side of the first memory cell material and a first side of the second memory cell material, and forming an electrode adjacent a second side of the first memory cell material and a second side of the second memory cell material.

Claims

1. A memory device, comprising:

at least two vertically stacked memory cells, wherein each of the memory cells include;

a memory cell material having a recess formed therein;

a first electrode in direct contact with a single first side of the memory cell material; and

a second electrode in the recess and in direct contact with a single second side of the memory cell material.

2. The memory device of claim 1, wherein the single first side is opposite the single second side.

3. The memory device of claim 1, wherein the memory cells include an insulator material adjacent a top and a bottom of the memory cell material.

4. The memory device of claim 3, wherein the insulator material is a nitride dielectric material.

5. The memory device of claim 1, wherein the memory cells are self-aligned memory cells.

6. The memory device of claim 1, wherein the first electrode includes an access device contact.

7. The memory device of claim 1, wherein the second electrode includes a metal material.

8. A memory device, comprising:

a first vertical stack of memory cells and a second vertical stack of memory cells, wherein each of the memory cells in the first and second vertical stacks include;

a memory cell material having a recess formed therein;

an access device contact in direct contact with a single first side of the memory cell material; and

a metal material in the recess and in direct contact with a single second side of the memory cell material.

9. The memory device of claim 8, wherein the memory cell material in the memory cells in the first and second vertical stacks is adjacent an access device contact.

10. The memory device of claim 8, wherein:

the memory cell material in the memory cells in the first vertical stack is adjacent a first access device contact; and

the memory cell material in the memory cells in the second vertical stack is adjacent a second access device contact.

11. The memory device of claim 8, wherein the memory cells in the first vertical stack are separated from the memory cells in the second vertical stack by an insulator material.

12. The memory device of claim 11, wherein the insulator material is an oxide dielectric material.

13. The memory device of claim 8, wherein the first and second vertical stacks include:

a first memory cell material;

a second memory cell material above the first memory cell material;

an access device contact adjacent a first side of the first memory cell material and a first side of the second memory cell material;

a first metal material adjacent a second side of the first memory cell material; and

a second metal material adjacent a second side of the second memory cell material.

14. A memory device, comprising:

a first vertical stack of resistive memory cells and a second vertical stack of resistive memory cells, wherein each resistive memory cell in the first and second vertical stacks includes;

a resistive memory cell material having a recess formed therein;

an electrode in direct contact with a single first side of the resistive memory cell material; and

an additional electrode in the recess and in direct contact with a single second side of the resistive memory cell material, wherein each resistive memory cell includes a portion of a different additional electrode.

15. The resistive memory device of claim 14, wherein the resistive memory cell material is phase change material.

16. The resistive memory device of claim 15, wherein the phase change material is a Germanium-Antimony-Tellurium material.

17. The resistive memory device of claim 14, wherein the resistive memory cell material is a resistive random access memory cell material.

18. The memory device of claim 14, wherein:

the electrode is an access device contact; and

the additional electrode is a metal line.

19. The memory device of claim 18, wherein the metal line is a data line.