Semiconductor device

• US 9,024,313 B2
• Filed: 04/11/2013
• Issued: 05/05/2015
• Est. Priority Date: 07/31/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Sakata, Junichiro, Ohara, Hiroki, Kuwabara, Hideaki
• Primary Examiner(s): YUSHIN, NIKOLAY K
• Application Number:
  US13/860,812
• Publication Number:
  US 20130234132A1
• Time in Patent Office: 754 Days
• Field of Search: 257/43, 257/59, 257/71
• US Class Current: 257/43
• CPC Class Codes: G06F 1/163 Wearable computers, e.g. on a belt
• CPC Class Codes: H01L 21/02614 Transformation of metal, e.g. oxidation, nitridation
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

One object is to provide a semiconductor device with a structure which enables reduction in parasitic capacitance sufficiently between wirings. In a bottom-gate type thin film transistor including a stacked layer of a first layer which is a metal thin film oxidized partly or entirely and an oxide semiconductor layer, the following oxide insulating layers are formed together: an oxide insulating layer serving as a channel protective layer which is over and in contact with a part of the oxide semiconductor layer overlapping with a gate electrode layer; and an oxide insulating layer which covers a peripheral portion and a side surface of the stacked oxide semiconductor layer.

Claims

1. A semiconductor device comprising:

a first transistor comprising;

a stacked layer including a first oxide semiconductor layer and a second oxide semiconductor layer, the stacked layer overlapped with a first gate electrode layer with a first insulating layer interposed therebetween; and

a second transistor comprising;

a third oxide semiconductor layer overlapped with a second gate electrode layer with a second insulating layer interposed therebetween,

wherein an oxide insulating layer covers and be in contact with a peripheral portion and a side surface of the stacked layer, and

wherein a source electrode layer and a drain electrode layer which are electrically connected to the second oxide semiconductor layer are provided over the oxide insulating layer.

2. The semiconductor device according to claim 1, further comprising a protective insulating layer in contact with the oxide insulating layer, the source electrode layer, the drain electrode layer, and the stacked layer,

wherein the protective insulating layer comprises any one of a silicon nitride, an aluminum nitride, a silicon nitride oxide, and an aluminum oxynitride.

3. The semiconductor device according to claim 1,

wherein the first oxide semiconductor layer and the second oxide semiconductor layer comprises materials different from each other, and

wherein the second oxide semiconductor layer and the third oxide semiconductor layer comprises a same material.

4. The semiconductor device according to claim 1, further comprising a capacitor portion,

wherein the capacitor portion comprises:

a capacitor wiring;

the first insulating layer in contact with the capacitor wiring; and

a capacitor electrode in contact with the first insulating layer,

wherein the capacitor electrode is overlapped with the capacitor wiring with the first insulating layer interposed therebetween.

5. The semiconductor device according to claim 1, wherein the side surface of the stacked layer is overlapped with the source electrode layer or the drain electrode layer with the oxide insulating layer interposed therebetween.

6. The semiconductor device according to claim 1, further comprising a wiring intersection of a gate wiring layer and a source wiring layer over a substrate,

wherein the gate wiring layer has a same potential as the first gate electrode layer,

wherein the source wiring layer has a same potential as the source electrode layer, and

wherein the first insulating layer and the oxide insulating layer are provided between the gate wiring layer and the source wiring layer in the wiring intersection.

7. The semiconductor device according to claim 1, wherein a width in a channel length direction of the first gate electrode layer is smaller than a width in the channel length direction of the first oxide semiconductor layer.

8. The semiconductor device according to claim 1,

wherein a width in a channel length direction of the first gate electrode layer is larger than a width in the channel length direction of the first oxide semiconductor layer, and

wherein a side surface of the first gate electrode layer overlaps with the source electrode layer or the drain electrode layer with the first insulating layer and the oxide insulating layer interposed therebetween.

9. The semiconductor device according to claim 1, wherein the source electrode layer and the drain electrode layer comprise any one of indium oxide, an alloy of indium oxide and tin oxide, an alloy of indium oxide and zinc oxide, and zinc oxide.

10. The semiconductor device according to claim 1, wherein the oxide insulating layer is a silicon oxide film or an aluminum oxide film formed by a sputtering method.

11. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer overlapped with the gate electrode layer with the gate insulating layer interposed therebetween;

an oxide insulating layer, wherein the oxide insulating layer covers and be in contact with a peripheral portion and a side surface of the oxide semiconductor layer; and

a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer, wherein the source electrode layer and the drain electrode layer are provided over the oxide insulating layer,

wherein the oxide semiconductor layer comprises a first region which comprises a channel formation region, and a second region other than the first region, and

wherein a first carrier concentration of the first region is lower than a second carrier concentration of the second region.

12. The semiconductor device according to claim 11,

wherein the first carrier concentration is lower than 1×

10¹⁸/cm³, and

wherein the second carrier concentration is higher than or equal to 1×

10¹⁸/cm³.

13. The semiconductor device according to claim 11, wherein the oxide semiconductor layer comprises In, Ga and Zn.

14. The semiconductor device according to claim 11, wherein the oxide semiconductor layer comprises a In—

Ga—

Zn—

O-based non-single-crystal oxide semiconductor.

15. The semiconductor device according to claim 11, wherein the oxide semiconductor layer has a thickness of 5 nm to 200 nm.

16. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer overlapped with the gate electrode layer with the gate insulating layer interposed therebetween;

an oxide insulating layer, wherein the oxide insulating layer covers and be in contact with a peripheral portion and a side surface of the oxide semiconductor layer; and

a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer, wherein the source electrode layer and the drain electrode layer are provided over the oxide insulating layer,

wherein the oxide semiconductor layer comprises a first region which comprises a channel formation region, and a second region other than the first region, and

wherein a first oxygen concentration of the first region is higher than a second oxygen concentration of the second region.

17. The semiconductor device according to claim 16, wherein a first resistance of the first region is higher than a second resistance of the second region.

18. The semiconductor device according to claim 16, wherein the first region is an i-type oxide semiconductor region.

19. The semiconductor device according to claim 16, wherein the oxide semiconductor layer comprises In, Ga and Zn.

20. The semiconductor device according to claim 16, wherein the oxide semiconductor layer comprises a In—

Ga—

Zn—

O-based non-single-crystal oxide semiconductor.

21. The semiconductor device according to claim 16, wherein the oxide semiconductor layer has a thickness of 5 nm to 200 nm.