Method and design of an RF thru-via interconnect

• US 9,024,326 B2
• Filed: 07/18/2012
• Issued: 05/05/2015
• Est. Priority Date: 07/18/2011
• Status: Active Grant

• Current Assignee: BAE Systems Information and Electronic Systems Integration Incorporated (BAE Systems Plc)
• Original Assignee: BAE Systems Information and Electronic Systems Integration Incorporated (BAE Systems Plc)
• Inventors: Actis, Robert, Chao, Pane-chane, Lender, Robert J. Jr., Chu, Kanin, Schmanski, Bernard J., Jessup, Sue May
• Primary Examiner(s): Dang, Trung Q
• Application Number:
  US13/879,696
• Publication Number:
  US 20130341644A1
• Time in Patent Office: 1,021 Days
• Field of Search: 257/76, 257/77, 438/584
• US Class Current: 257/76
• CPC Class Codes: H01L 2223/6622 Coaxial feed-throughs in active or passive substrates
• CPC Class Codes: H01L 2223/6627 Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 2224/4847 the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
• CPC Class Codes: H01L 23/373 Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/10272 Silicon Carbide [SiC]
• CPC Class Codes: H01L 2924/1033 Gallium nitride [GaN]
• CPC Class Codes: H01L 2924/1421 RF devices
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 2924/30111 matching

Abstract

In summary, a vertical metalized transition in the form of a via goes from the back side of a high thermal conductivity substrate and through any semiconductor layers thereon to a patterned metalized strip, with the substrate having a patterned metalized layer on the back side that is provided with a keep away zone dimensioned to provide impedance matching for RF energy coupled through the substrate to the semiconductor device while at the same time permitting the heat generated by the semiconductor device to flow through the high thermal conductivity substrate, through the back side of the substrate and to a beat sink.

Claims

1. In a method of forming a semiconductor RF connection for improved thermal management on a semiconductor chip, wherein the improvement comprises:

forming a vertical transition passing through the semiconductor chip;

connecting RF signals through the back of the semiconductor chip at the vertical transition, enabling backside heat sinking, wherein the back of the chip comprises a patterned metalized layer having a keep away surrounding the base of the vertical transition for impedance matching.

2. The method according to claim 1, wherein the semiconductor chip is a GaN chip.

3. In a semi-conductor device having a high thermal conductivity substrate and a semiconductor layer thereon onto which is patterned a semi-conductor device, a system for providing an RF connection to an electrode associated with said semi-conductor device comprising:

a vertical transition through said high thermal conductivity substrate, said vertical transition including a metalized via through the back side thereof and through said layer, said substrate including a metallization layer on the back side thereof, said metalized layer having a keep away region surrounding the lower end of said via, whereby heat generated at said semiconductor device propagates through said high thermal conductivity substrate and through said metallization layer, such that said metallization layer and said metalized via comprise an RF port for impedance matched transmission of externally generated RF signals through said substrate and said semiconductor layer to said electrode.

4. The system of claim 3, wherein said substrate includes silicon carbide.

5. The system of claim 4, wherein said semiconductor layer includes gallium nitride.

6. The system of claim 3, wherein the impedance of said port is 50 ohms.

7. The system of claim 3, wherein said semiconductor device includes a transistor having a gate electrode and wherein the heat generated by the operation of said transistor occurs in the vicinity of said gate electrode.

8. The system of claim 3, and further including a heat sink in contact with the metallization on the back side of said substrate.

9. The system of claim 3, wherein said metallization layer has a keep away zone surrounding the base of said via and is spaced from the metalized walls of said via by a predetermined distance such that said port has a controllable impedance.

10. The system of claim 9, wherein the metalized walls of said via are in a rectilinear configuration in which two opposed sidewalls and an adjacent sidewall are spaced from the periphery of said keep away zone by a pre-determined distance, and wherein a sidewall opposed to the said adjacent side wall is spaced from the keep away zone periphery by a distance less than that of the distance associated with the other side walls.

11. The system of claim 10, wherein the first of said distances is 100 microns and the second of said distances is 70 microns.

13. The system of claim 3, and further including a coaxial transmission line having a central pin conductor that extends therefrom and is adapted to be positioned within said via.

14. The system of claim 13, wherein the sidewalls of said via are rectilinear and wherein said central pin has a rectilinear configuration.

15. The system of claim 14, wherein said rectilinear pin is adapted to be received within the metalized side walls of said via in a tight fit.

16. The system of claim 15, wherein said coaxial transmission line has a rectilinear outer conductor, said rectilinear outer conductor being stripped back from the said central pin and is adapted to contact said metalized layer on the back of said high thermal conductivity substrate when said pin is inserted into said wall-metalized via.

17. The system of claim 3, and further including a patterned metalized strip on top of said semi-conductor layer, said patterned metalized strip overlying said via and in electrical contact with the metalized walls of said via.

18. The system of claim 17, wherein said semiconductor device has an electrode and wherein said patterned metalized strip extends from said via to said electrode.

12. The system of 11, wherein the width dimension of each of said sidewalls is 120 microns.