Device structure and manufacturing method using HDP deposited source-body implant block

• US 9,024,378 B2
• Filed: 02/09/2013
• Issued: 05/05/2015
• Est. Priority Date: 02/09/2013
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bhalla, Anup, Hbert, Franois, Tai, Sung-Shan, Lui, Sik K
• Primary Examiner(s): Weiss, Howard
• Assistant Examiner(s): TANG, SUIAN
• Application Number:
  US13/763,644
• Publication Number:
  US 20140225187A1
• Time in Patent Office: 815 Days
• Field of Search: 257330-332, 257/E21.258, 438/206, 438/272, 438/478, 438/531, 438498-499
• US Class Current: 257/330
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

Claims

1. A method for manufacturing a trenched semiconductor power device comprising:

applying a trench mask for opening a plurality of trenches from a top surface of a semiconductor substrate by configuring the trench mask having a greater distance between two adjacent trenches in a termination area than an active cell area and forming a thick insulation layer covering over trench sidewalls and a bottom surface of said trenches and also simultaneously covering over the top surface of the semiconductor substrate outside of the trenches;

applying an implanting-ion block mask for etching the thick insulation layer from a top part of the trenches and the trench sidewalls and also simultaneously from an area surrounding the trenches thus leaving a thick bottom insulation layer at a bottom portion of the trenches and implanting-ion blocks above said top surface in a mesa area between and at a distance away from said trenches and in a middle portion between two of said trenches for blocking body implanting ions and source ions from entering into said substrate under said mesa area whereby masks for manufacturing said semiconductor power device can be reduced; and

implanting body dopant ions and source dopant ions with said implanting-ion block blocking said mesa area in the middle portion between two of said trenches to form body regions encompassing source regions and forming the body regions in the termination area as floating body regions to function as guard rings for the semiconductor power device.

2. The method of claim 1 wherein:

the step of forming the thick insulation layer further comprising a step of forming an oxide layer having a thickness larger than 0.3 microns.

3. The method of claim 1 wherein:

the step of forming the thick insulation layer further comprising a step of applying a HDP deposition process to form an HDP oxide layer covering over trench sidewalls and the bottom surface of said trenches and also covering over the top surface of the semiconductor substrate outside of the trenches.

4. The method of claim 1 wherein:

the step of forming the thick insulation layer further comprising a step of applying a high-density plasma (HDP) deposition process for depositing a thick oxide layer covering a bottom surface of said trenches and also covering over the top surface of the semiconductor substrate outside of the trenches having a thickness larger than 0.3 microns and greater than a thickness of the insulation layer covering the trench sidewalls having a thickness larger than 0.3 microns and greater than a thickness of the insulation layer covering the trench sidewalls.

5. The method of claim 1 wherein:

the step of forming the thick insulation layer further comprising a step of applying a chemical vapor deposition (CVD) to form an oxide layer covering over trench sidewalls and the bottom surface of said trenches and also covering over the top surface of the semiconductor substrate outside of the trenches.

6. The method of claim 1 wherein:

the step of forming said thick insulation layer further comprising a step of applying a thermal oxidation to form an oxide layer covering over trench sidewalls and the bottom surface of said trenches and also covering over the top surface of the semiconductor substrate outside of the trenches.

7. A method for manufacturing a trenched semiconductor power device comprising:

applying a trench mask for opening a plurality of trenches from a top surface of a semiconductor substrate by configuring the trench mask having a greater distance between two adjacent trenches in a termination area than an active cell area and forming a thick insulation layer covering over trench sidewalls and a bottom surface of said trenches and also simultaneously covering over the top surface of the semiconductor substrate outside of the trenches;

applying an implanting-ion block mask for etching the thick insulation layer from a top part of the trenches and the trench sidewalls and also simultaneously from an area surrounding the trenches thus leaving a thick bottom insulation layer at a bottom portion of the trenches and implanting-ion blocks above said top surface in a mesa area between and at a distance away from said trenches and in a middle portion between two of said trenches for blocking body implanting ions and source ions from entering into said substrate under said mesa area whereby masks for manufacturing said semiconductor power device can be reduced; and

implanting body dopant ions with said implanting-ion block and followed by applying a source ion implant mask for implanting source dopant ions to form body regions encompassing source regions adjacent to the mesa area in the middle portion between two of said trenches and forming the body regions in the termination area as floating body regions and having no source regions therein to function as guard rings for the semiconductor power device.

8. The method of claim 7 wherein:

the step of forming the thick insulation layer further comprising a step of forming an oxide layer having a thickness larger than 0.3 microns.

9. The method of claim 7 wherein:

the step of forming the thick insulation layer further comprising a step of applying a HDP deposition process to form an HDP oxide layer covering over trench sidewalls and the bottom surface of said trenches and also covering over the top surface of the semiconductor substrate outside of the trenches.

10. The method of claim 7 wherein:

the step of forming the thick insulation layer further comprising a step of applying a high-density plasma (HDP) deposition process for depositing a thick oxide layer covering bottom surface of said trenches and also covering over the top surface of the semiconductor substrate outside of the trenches having a thickness larger than 0.3 microns and greater than a thickness of the insulation layer covering the trench sidewalls having a thickness larger than 0.3 microns and greater than a thickness of the insulation layer covering the trench sidewalls.

11. The method of claim 7 wherein:

the step of forming the thick insulation layer further comprising a step of applying a chemical vapor deposition (CVD) to form an oxide layer covering over trench sidewalls and the bottom surface of said trenches and also covering over the top surface of the semiconductor substrate outside of the trenches.

12. The method of claim 7 wherein:

the step of forming said thick insulation layer further comprising a step of applying a thermal oxidation to form an oxide layer covering over trench sidewalls and the bottom surface of said trenches and also covering over the top surface of the semiconductor substrate outside of the trenches.

13. A method for manufacturing a trenched semiconductor power device comprising:

applying a trench mask for opening a plurality of trenches from a top surface of a semiconductor substrate by configuring the trench mask having a greater distance between two adjacent trenches in a termination area than an active cell area and forming a thick insulation layer covering over trench sidewalls and a bottom surface of said trenches and also simultaneously covering over the top surface of the semiconductor substrate outside of the trenches;

applying an implanting-ion block mask for etching the thick insulation layer from a top part of the trenches and the trench sidewalls and also simultaneously from an area surrounding the trenches thus leaving a thick bottom insulation layer at a bottom portion of the trenches and implanting-ion blocks above said top surface in a mesa area between and at a distance away from said trenches and in a middle portion between two of said trenches for blocking body implanting ions and source ions from entering into said substrate under said mesa area whereby masks for manufacturing said semiconductor power device can be reduced; and

implanting P-type body dopant ions with said implanting-ion block and followed by applying a source ion implant mask for implanting N-type source dopant ions to form P-type body regions encompassing N-type source regions adjacent to the mesa area with said implanting-ion block and forming the P-type body regions in the termination area as floating body regions and having no source regions therein to function as guard rings for the semiconductor power device.

14. The method of claim 13 wherein:

the step of forming the thick insulation layer further comprising a step of forming an oxide layer having a thickness larger than 0.3 microns.

15. The method of claim 13 wherein:

the step of forming the thick insulation layer further comprising a step of applying a HDP deposition process to form an HDP oxide layer covering over trench sidewalls and the bottom surface of said trenches and also covering over the top surface of the semiconductor substrate outside of the trenches.

16. The method of claim 13 wherein:

the step of forming the thick insulation layer further comprising a step of applying a high-density plasma (HDP) deposition process for depositing a thick oxide layer covering bottom surface of said trenches and also covering over the top surface of the semiconductor substrate outside of the trenches having a thickness larger than 0.3 microns and greater than a thickness of the insulation layer covering the trench sidewalls having a thickness larger than 0.3 microns and greater than a thickness of the insulation layer covering the trench sidewalls.

17. The method of claim 13 wherein:

the step of forming the thick insulation layer further comprising a step of applying a chemical vapor deposition (CVD) to form an oxide layer covering over trench sidewalls and the bottom surface of said trenches and also covering over the top surface of the semiconductor substrate outside of the trenches.

18. The method of claim 13 wherein:

the step of forming said thick insulation layer further comprising a step of applying a thermal oxidation to form an oxide layer covering over trench sidewalls and the bottom surface of said trenches and also covering over the top surface of the semiconductor substrate outside of the trenches.