Semiconductor device

• US 9,024,382 B2
• Filed: 02/24/2011
• Issued: 05/05/2015
• Est. Priority Date: 02/26/2010
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kitagawa, Mitsuhiko
• Primary Examiner(s): Jackson, Jr., Jerome
• Application Number:
  US13/034,443
• Publication Number:
  US 20110210391A1
• Time in Patent Office: 1,531 Days
• Field of Search: 257/342
• US Class Current: 257/342
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

According to one embodiment, the semiconductor device includes a drift region, a first semiconductor region, a second semiconductor region, a main electrode, first gate electrodes and a second gate electrode. The first gate electrodes and the second gate electrode between a pair of first gate electrodes are provided in the drift region. The first semiconductor region is provided between the first gate electrodes and the second gate electrode. The first semiconductor region has a first side surface opposite to the one of the adjacent ones and a second side surface partially opposite to the second gate electrode. The second semiconductor region is selectively provided on the first semiconductor region. The main electrode has a portion directly adjacent to part of the second side surface and the second semiconductor region.

Claims

1. A semiconductor device comprising:

a drift region including a semiconductor of a first conductivity type;

a pair of first gate electrodes contacting the drift region via a first gate insulating film and extending in a first direction into the drift region;

a second gate electrode contacting the drift region via a second gate insulating film and extending in the first direction into the drift region, the second gate electrode positioned between the pair of first gate electrodes in a second direction perpendicular to the first direction;

a first semiconductor region of a second conductivity type between each of the first gate electrodes and the second gate electrode in the second direction;

a second semiconductor region of the first conductivity type selectively provided on the first semiconductor region, and adjacent via the first gate insulating film to one of the first gate electrodes in the pair of first gate electrodes; and

a main electrode having a first portion that is adjacent in the first direction to the pair of first gate electrodes via the first gate insulating film, and a second portion between the pair of first gate electrodes that is adjacent in the first direction to the second gate electrode via the second gate insulating film, and directly adjacent in the second direction to the first semiconductor region and the second semiconductor region.

2. The device according to claim 1, wherein

a width, along the first direction, of the second portion of the main electrode that is in contact with the first semiconductor region is 0.05 μ

m or more.

3. The device according to claim 1, further comprising:

a sixth semiconductor region of the second conductivity type between the first semiconductor region and the main electrode in the first direction, wherein

the second semiconductor region and the sixth semiconductor region are alternately provided in contact with the first semiconductor region along a third direction orthogonal to the first and second directions.

4. The device according to claim 1, further comprising:

a sixth semiconductor region of the second conductivity type between the first semiconductor region and the main electrode in the first direction, wherein

the second semiconductor region is in contact with the first semiconductor region and extended along the one of the pair of first gate electrodes in the first direction, and the sixth semiconductor region is in contact with the first semiconductor region and extended along one of the pair of the first gate electrodes in the first direction.

5. The device according to claim 1, further comprising:

a third semiconductor region of the second conductivity type that is selectively provided on the first semiconductor region, wherein the third semiconductor region has a concentration of the second conductivity type impurities that is greater than a concentration of second conductivity type impurities in the first semiconductor region, and

the main electrode is directly adjacent the third semiconductor region in the second direction.

6. The device according to claim 1, wherein

the drift region includes a fourth semiconductor region of the first conductivity type and a fifth semiconductor region of the second conductivity type that are alternately provided along a boundary between the drift region and the first semiconductor region.

7. The device according to claim 1, further comprising:

a seventh semiconductor region of the second conductivity type provided adjacently to the drift region, the drift region being between the first semiconductor region and the seventh semiconductor region.

8. The device according to claim 1, further comprising:

an insulating layer in contact with the drift region and the first semiconductor region, wherein

the drift region and the first semiconductor region are provided adjacently on the main surface of the insulating layer.

9. The device according to claim 8, wherein

the drift region includes a fourth semiconductor region of the first conductivity type and a fifth semiconductor region of the second conductivity type alternately provided in a direction parallel with the main surface of the insulating layer along a boundary between the drift region and the first semiconductor region.

10. The device according to claim 8, wherein

the drift region includes a fourth semiconductor region of the first conductivity type and a fifth semiconductor region of the second conductivity type alternately laminated on the insulating layer.

11. The device according to claim 8, further comprising:

a sixth semiconductor region of the second conductivity type between the first semiconductor region and the main electrode, wherein

the second semiconductor region and the sixth semiconductor region are alternately provided on the insulating layer.

12. The device according to claim 8, wherein

the insulating film is one of a semi-insulating layer and a SiO₂ film provided on a substrate.

13. The device according to claim 1, wherein

the drift region is on a first main surface of a semiconductor layer of the first conductivity type;

the first semiconductor region is in the drift region;

the second semiconductor region is in the first semiconductor region; and

the main electrode is in contact with the second semiconductor region in a trench communicating with the first semiconductor region from a surface of the second semiconductor region.

14. The device according to claim 13, wherein

the pair of first gate electrodes and the second gate electrode penetrate through the first semiconductor region in the first direction.

15. The device according to claim 13, wherein

the pair of first gate electrode and the second gate electrode penetrate through the first semiconductor region and the drift region in the first direction.

16. The device according to claim 8, wherein

the drift region includes a fourth semiconductor region of the first conductivity type and a fifth semiconductor region of the second conductivity type alternately laminated on the insulating layer;

and

the first semiconductor region includes an eighth semiconductor region of the first conductivity type and a ninth semiconductor region of the second conductivity type alternately laminated on the insulating layer.

17. The device according to claim 16, wherein

a width of the eighth semiconductor region in the lamination direction is smaller than the width of the ninth semiconductor region in the lamination direction.