Local interconnect structures for high density

• US 9,024,418 B2
• Filed: 03/14/2013
• Issued: 05/05/2015
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Zhu, John Jianhong, Nallapati, Giridhar, Chidambaram, PR
• Primary Examiner(s): Potter, Roy
• Assistant Examiner(s): PATTON, PAUL E
• Application Number:
  US13/829,864
• Publication Number:
  US 20140264629A1
• Time in Patent Office: 782 Days
• Field of Search: 257/758
• US Class Current: 257/666
• CPC Class Codes: H01L 21/76841 Barrier, adhesion or liner layers
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A local interconnect structure is provided that includes a gate-directed local interconnect coupled to an adjacent gate layer through a diffusion-directed local interconnect.

Claims

1. A circuit comprising:

a first gate layer arranged according to a gate layer pitch between a second gate layer and a third gate layer;

a first gate-directed local interconnect arranged between the first gate layer and the second gate layer;

a second gate-directed local interconnect arranged between the first gate layer and the third gate layer; and

a diffusion-directed local interconnect layer configured to couple the first gate layer to one of the first and second gate-directed local interconnects, wherein the first gate-directed local interconnect, the second gate-directed local interconnect, and the diffusion-directed local interconnect are all located between a lower-most metal layer and a semiconductor substrate for the circuit.

2. The circuit of claim 1, further comprising a continuous diffusion region, wherein the first gate layer comprises a gate for a blocking transistor formed in the continuous diffusion region, and wherein the first gate-directed local interconnect is configured to couple to a first source/drain terminal for an adjacent first transistor and wherein the second gate-directed local interconnect is configured to couple to a second drain/source terminal for an adjacent second transistor.

3. The circuit of claim 2, wherein the diffusion-directed local interconnect layer is positioned outside of a footprint for the continuous diffusion region.

4. The circuit of claim 1, wherein the diffusion-directed local interconnect layer is positioned within a footprint for the continuous diffusion region.

5. The circuit of claim 2, wherein the diffusion-directed local interconnect layer is configured to couple the first gate-directed local interconnect to the first gate layer, the circuit further comprising a via coupled between a first metal layer and the first gate-directed interconnect layer to couple the first gate layer for the second transistor to a power supply node.

6. The circuit of claim 2, wherein the first gate-directed local interconnect, the second gate-directed local interconnect, and the diffusion-directed local interconnect are each level 2 interconnects, the circuit further comprising a first level 1 gate-directed local interconnect arranged between the first level 2 gate-directed local interconnect and the first source/drain terminal to couple the first level 2 gate-directed local interconnect to the first source/drain terminal.

7. The circuit of claim 1, wherein the first gate-directed local interconnect, the second gate-directed local interconnect, and the diffusion-directed local interconnect all comprise tungsten.

8. The circuit of claim 1, wherein the first gate layer is the gate layer for a diode-connected transistor.

9. The circuit of claim 8, further comprising a continuous diffusion region including drain/source terminals for the diode-connected transistor, and wherein the diffusion-directed local interconnect is located outside of a footprint for the continuous diffusion region.

10. The circuit of claim 1, wherein the first gate layer is a gate layer for a first inverter, and wherein the one of the first and second gate-directed local interconnects is a gate-directed local interconnect for an output node for a second inverter.

11. The circuit of claim 1, further comprising:

a fourth gate layer separated from the first gate layer by a gate cut layer, wherein the one of the first and second gate-directed local interconnects is configured to extend across the gate cut layer; and

a second diffusion-directed local interconnect configured to couple the one of the first and second gate-directed local interconnects to the fourth gate layer.

12. A method, comprising:

forming a first gate layer over a semiconductor substrate according to a gate layer pitch between adjacent second and third gate layers;

forming a first gate-directed local interconnect between the first gate layer and the second gate layer;

forming a second gate-directed local interconnect between the first gate layer and the third gate layer; and

forming a diffusion-directed local interconnect to couple one of the first and second gate-connected local interconnects to the first gate layer, wherein the first gate-directed local interconnect, the second gate-directed local interconnect, and the diffusion-directed local interconnect are all located between the semiconductor substrate and an adjacent lower-most metal layer.

13. The method of claim 12, wherein forming the first gate layer forms a gate for a blocking transistor.

14. The method of claim 13, further comprising forming a continuous diffusion region, wherein forming the first gate layer forms a gate for a transistor having a pair of drain/source terminals in the continuous diffusion region, and wherein forming the diffusion-directed local interconnect comprises forming the diffusion-directed local interconnect outside of a footprint for the continuous diffusion region.

15. The method of claim 13, further comprising forming a continuous diffusion region, wherein forming the first gate layer forms a gate for a transistor having a pair of drain/source terminals in the continuous diffusion region, and wherein forming the diffusion-directed local interconnect comprises forming the diffusion-directed local interconnect within a footprint for the continuous diffusion region.

16. The method of claim 12, further comprising forming a via coupled between the one of the first and second gate-directed local interconnects and a first metal layer.

17. A circuit comprising:

a continuous diffusion region within a semiconductor substrate;

a pair of gate layers configured to form gates for a pair of transistors having source/drain terminals in the continuous diffusion region;

a third gate layer arranged between the pair of gate layers to form a gate for a blocking transistor;

a gate-directed local interconnect configured to couple to a drain/source terminal for a transistor in the pair of transistors; and

means for coupling the gate-directed local interconnect to the third gate layer, wherein the gate-directed local interconnect and the means are both located between the semiconductor substrate and an adjacent lower-most metal layer.

18. The circuit of claim 17, wherein the continuous diffusion region is a p-type diffusion region, and wherein the means for coupling the gate-directed local interconnect to the third gate layer is configured to couple the third gate layer to a supply voltage VDD.

19. The circuit of claim 17, wherein the continuous diffusion region is a n-type diffusion region, and wherein the means for coupling the gate-directed local interconnect to the third gate layer is configured to couple the third gate layer to ground.

20. The circuit of claim 17, wherein the means is formed within a footprint for the continuous diffusion region.