Power quad flat no-lead (PQFN) package

• US 9,024,420 B2
• Filed: 11/11/2013
• Issued: 05/05/2015
• Est. Priority Date: 12/13/2010
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Fernando, Dean, Barbosa, Roel
• Primary Examiner(s): Gumedzoe, Peniel M
• Application Number:
  US14/076,467
• Publication Number:
  US 20140061885A1
• Time in Patent Office: 540 Days
• Field of Search: 257/578, 257/677, 257/690, 257/723, 257/E23.31, 257/E23.042, 257/E23.051, 257/E23.061, 257/676
• US Class Current: 257/676
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4903 Connectors having different sizes, e.g. different diameters
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49513 having bonding material between chip and die pad
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18301 : being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
• CPC Class Codes: H01L 2924/20753 : larger or equal to 30 microns less than 40 microns
• CPC Class Codes: H01L 2924/20755 : larger or equal to 50 microns less than 60 microns
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes.

Claims

1. A power quad flat no-lead (PQFN) semiconductor package comprising:

a leadframe comprising a plurality of die pads;

a driver integrated circuit (IC) coupled to a top surface of a first die pad of said leadframe;

a plurality of vertical conduction power transistors including a first group of vertical conduction power transistors coupled to a top surface of a common die pad of said leadframe and a second group of vertical conduction power transistors individually coupled to respective top surfaces of separate die pads of said leadframe;

a top surface electrode of one of said first group of vertical conduction power transistors being electrically connected to a bottom surface electrode of one of said second group of vertical conduction power transistors;

at least one wirebond providing direct electrical connection between said driver IC and one of said plurality of vertical conduction power transistors;

wherein each of said first die pad, said common die pad and said separate die pads has a separate exposed surface on a bottom surface of said leadframe.

2. The PQFN semiconductor package of claim 1, wherein said PQFN semiconductor package is configured as a full bridge power device.

3. The PQFN semiconductor package of claim 1, wherein said leadframe is selectively plated with silver for enhanced adhesion.

4. The PQFN semiconductor package of claim 1, wherein said first group of vertical conduction power transistors is positioned near a first edge of said package, and wherein said second group of vertical conduction power transistors is positioned near a second edge of said package.

5. The PQFN semiconductor package of claim 1, wherein a footprint of the package is 12 mm by 12 mm or greater.

6. The PQFN semiconductor package of claim 1, wherein said plurality of vertical conduction power transistors comprises power MOSFETs.

7. The PQFN semiconductor package of claim 1, wherein said plurality of vertical conduction power transistors comprises IGBTs.

8. A power quad flat no-lead (PQFN) semiconductor package comprising:

a leadframe;

a driver integrated circuit (IC) coupled to a top surface of a first die pad of said leadframe;

a plurality of vertical conduction power transistors including a plurality of high side transistors coupled to a top surface of a common die pad of said leadframe and a plurality of low side transistors coupled to respective top surfaces of individual die pads of said leadframe, a top surface electrode of one of said plurality of vertical conduction power transistors being electrically connected to a portion of said leadframe, wherein said portion of said leadframe is electrically connected to a bottom surface electrode of another of said plurality of vertical conduction power transistors;

at least one wirebond providing direct electrical connection between said driver IC and a first of said plurality of vertical conduction power transistors;

wherein each of said first die pad, said common die pad and said individual die pads has a separate exposed surface on a bottom surface of said leadframe.

9. The PQFN semiconductor package of claim 8, wherein said PQFN semiconductor package is configured as a full bridge power device.

10. The PQFN semiconductor package of claim 8, wherein said leadframe is selectively plated with silver for enhanced adhesion.

11. The PQFN semiconductor package of claim 8, wherein a footprint of the package is 12 mm by 12 mm or greater.

12. The PQFN semiconductor package of claim 8, wherein said plurality of vertical conduction power transistors has six (6) vertical conduction power transistors.

13. The PQFN semiconductor package of claim 8, wherein said plurality of vertical conduction power transistors comprises power MOSFETs.

14. The PQFN semiconductor package of claim 8, wherein said plurality of vertical conduction power transistors comprises IGBTs.

15. A power quad flat no-lead (PQFN) semiconductor package comprising:

a leadframe;

a driver integrated circuit (IC) coupled to a top surface of a first die pad of said leadframe;

a plurality of vertical conduction power transistors including a first group of vertical conduction power transistors coupled to a top surface of a common die pad and a second group of vertical transistors coupled to respective top surfaces of individual die pads of said leadframe, a top surface electrode of one of said plurality of vertical conduction power transistors being electrically connected to a portion of said leadframe, wherein said portion of said leadframe is electrically connected to a bottom surface electrode of another of said plurality of vertical conduction power transistors;

at least one wirebond providing direct electrical connection between said driver IC and a first of said plurality of vertical conduction power transistors;

wherein each of said first die pad, said common die pad and said individual die pads has a separate exposed surface on a bottom surface of said leadframe.

16. The PQFN semiconductor package of claim 15, wherein said PQFN semiconductor package is configured as a full bridge power device.

17. The PQFN semiconductor package of claim 15, wherein said plurality of vertical conduction power transistors is divided into said first group positioned on said common die pad near a first edge of said PQFN semiconductor package and said second group positioned on said individual die pads near a second edge of said PQFN semiconductor package, said first group including said one of said plurality of vertical conduction power transistors and said second group including said another of said plurality of vertical conduction power transistors.

18. The PQFN semiconductor package of claim 15, wherein a footprint of the package is 12 mm by 12 mm or greater.

19. The PQFN semiconductor package of claim 15, wherein said plurality of vertical conduction power transistors comprises power MOSFETs.

20. The PQFN semiconductor package of claim 15, wherein said plurality of vertical conduction power transistors comprises IGBTs.