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PWM control apparatus for average output current balancing in multi-stage DC-DC converters

  • US 9,024,600 B2
  • Filed: 07/23/2013
  • Issued: 05/05/2015
  • Est. Priority Date: 10/10/2012
  • Status: Active Grant
First Claim
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1. An integrated circuit for providing pulse width modulation control of a DC-DC converter stage in a multi-stage DC-DC conversion system, the integrated circuit comprising:

  • a balancing circuit, including;

    a first amplifier circuit with an input receiving a voltage signal representing a converter stage output current, the first amplifier circuit providing a first amplifier circuit output,a current mirror circuit, including;

    a first transistor providing a first current output at a first current mirror output node based on the first amplifier circuit output, the first current mirror output node being connected to a balancing voltage input terminal to receive a voltage signal from at least one other converter stage of the multi-stage DC-DC conversion system, anda second transistor providing a second current output at a second current mirror output node based on the first amplifier circuit output,a first resistor connected between the first current mirror node and a circuit ground node,a second resistor connected between the second current mirror node and the circuit ground node, anda transconductance amplifier with first and second inputs respectively connected to the first and second current mirror output nodes and a transconductance amplifier output controlling a correction current output signal based on a difference between the voltages at the first and second current mirror nodes;

    a reference circuit with a reference circuit output providing a reference current based on a received input voltage and on a value of a resistor, and a correction output providing the correction current based on the received input voltage, the value of the resistor, and a correction control signal;

    an internal node connected to the reference circuit output and the correction output; and

    a pulse generator circuit, including;

    a capacitance with a first terminal connected to the internal node, and a second terminal connected to the circuit ground node,a switch circuit operative in a first state to discharge the capacitance according to a switch control signal,a comparator with a first input terminal connected to the internal node, a second input terminal connected to a threshold voltage, and a comparator output providing a pulse signal at a first level when a voltage across the capacitance is greater than the threshold voltage and a second level when the voltage across the capacitance is less than the threshold voltage, anda flip-flop with a first input connected to the comparator output, a second input receiving a trigger signal to begin a new pulse width modulation period, a first output providing a pulse width modulation output signal for control of the DC-DC converter stage, and a complementary second output providing the switch control signal to place the switch circuit in the first state to discharge the capacitance to begin the new pulse width modulation period.

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