Storage element, storage device, and signal processing circuit

• US 9,024,669 B2
• Filed: 10/31/2013
• Issued: 05/05/2015
• Est. Priority Date: 01/05/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ohmaru, Takuro, Endo, Masami
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): HUERTA, PABLO S
• Application Number:
  US14/068,217
• Publication Number:
  US 20140048802A1
• Time in Patent Office: 551 Days
• Field of Search: 365/208
• US Class Current: 327/208
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 14/0009 in which the volatile element is a DRAM cell
• CPC Class Codes: G11C 19/184 with field-effect transistors, e.g. MOS-FET
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/26 including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24 , e.g. alloys
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.

Claims

1. A storage device comprising:

a first storage element; and

a second storage element,

wherein at least one of the first storage element and the second storage element comprises;

a storage circuit;

a first transistor;

a second transistor;

a third transistor; and

a capacitor,

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor material,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein one of a pair of electrodes of the capacitor is electrically connected to the one of the source and the drain of the first transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to the storage circuit, and

wherein the other of the source and the drain of the third transistor is electrically connected to the storage circuit.

2. The storage device according to claim 1, wherein the storage circuit is configured to hold data only in a period during which a power supply voltage supplied.

3. The storage device according to claim 1, wherein the other of the source and the drain of the first transistor is electrically connected to an output terminal of the storage circuit.

4. The storage device according to claim 1, wherein the other of the source and the drain of the third transistor is electrically connected to an input terminal of the storage circuit.

5. The storage device according to claim 1, further comprising a fourth transistor, one of a source and a drain of the fourth transistor being electrically connected to the other of the source and the drain of the third transistor.

6. The storage device according to claim 5, wherein a gate of the third transistor is electrically connected to a gate of the fourth transistor.

7. The storage device according to claim 5, wherein the other of the source and the drain of the fourth transistor is electrically connected to a power supply line.

8. The storage device according to claim 1, wherein a control signal is input to a gate of the third transistor.

9. The storage device according to claim 1, wherein the other of the source and the drain of the third transistor is electrically connected to the storage circuit through an inverter and a switch.

10. The storage device according to claim 1, further comprising a fifth transistor configured to control a supply of a power supply voltage to the first storage element and the second storage element.

11. The storage device according to claim 10, wherein the fifth transistor comprises a channel formation region comprising an oxide semiconductor material.

12. A storage device comprising:

a first storage element;

a second storage element; and

a first transistor configured to control a supply of a power supply voltage to the first storage element and the second storage element,

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor material,

wherein at least one of the first storage element and the second storage element comprises;

a second transistor; and

a third transistor comprising a channel formation region, the channel formation region comprising an oxide semiconductor material, wherein one of a source and a drain of the third transistor is electrically connected to a gate of the second transistor.

13. The storage device according to claim 12, wherein each of the oxide semiconductor material of the first transistor and the oxide semiconductor material of the third transistor is an In—

Ga—

Zn-based oxide.

14. The storage device according to claim 12, wherein each of the oxide semiconductor material of the first transistor and the oxide semiconductor material of the third transistor is an In—

Sn—

Zn-based oxide.

15. The storage device according to claim 12, wherein the power supply voltage is VDD.

16. The storage device according to claim 12, wherein the power supply voltage is VSS.

17. The storage device according to claim 12, further comprising a capacitor, one of a pair of electrodes of the capacitor being electrically connected to the one of the source and the drain of the third transistor.

18. A storage device comprising:

a first storage element;

a second storage element; and

a first transistor configured to control a supply of a power supply voltage to the first storage element and the second storage element,

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor material,

wherein at least one of the first storage element and the second storage element comprises;

a second transistor;

a third transistor comprising a channel formation region, the channel formation region comprising an oxide semiconductor material, wherein one of a source and a drain of the third transistor is electrically connected to a gate of the second transistor; and

a storage circuit configured to hold data only in a period during which a power supply voltage supplied.

19. The storage device according to claim 18, wherein each of the oxide semiconductor material of the first transistor and the oxide semiconductor material of the third transistor is an In—

Ga—

Zn-based oxide.

20. The storage device according to claim 18, wherein each of the oxide semiconductor material of the first transistor and the oxide semiconductor material of the third transistor is an In—

Sn—

Zn-based oxide.

21. The storage device according to claim 18, wherein the power supply voltage whose supply is controlled by the first transistor is VDD.

22. The storage device according to claim 18, wherein the power supply voltage whose supply is controlled by the first transistor is VSS.

23. The storage device according to claim 18, further comprising a capacitor, one of a pair of electrodes of the capacitor being electrically connected to the one of the source and the drain of the third transistor.

24. The storage device according to claim 18, wherein the other of the source and the drain of the third transistor is electrically connected to the storage circuit.

25. A storage device comprising:

a storage circuit;

a first transistor;

a second transistor;

a third transistor; and

a capacitor,

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor material,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein one of a pair of electrodes of the capacitor is electrically connected to the one of the source and the drain of the first transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to the storage circuit, and

wherein the other of the source and the drain of the third transistor is electrically connected to the storage circuit.

26. The storage device according to claim 25, wherein the storage circuit is configured to hold data only in a period during which a power supply voltage supplied.

27. The storage device according to claim 25, wherein the other of the source and the drain of the first transistor is electrically connected to an output terminal of the storage circuit.

28. The storage device according to claim 25, wherein the other of the source and the drain of the third transistor is electrically connected to an input terminal of the storage circuit.

29. The storage device according to claim 25, further comprising a fourth transistor, one of a source and a drain of the fourth transistor being electrically connected to the other of the source and the drain of the third transistor.

30. The storage device according to claim 29, wherein a gate of the third transistor is electrically connected to a gate of the fourth transistor.

31. The storage device according to claim 29, wherein the other of the source and the drain of the fourth transistor is electrically connected to a power supply line.

32. The storage device according to claim 25, wherein the other of the source and the drain of the third transistor is electrically connected to the storage circuit through an inverter and a switch.

33. The storage device according to claim 25, wherein a control signal is input to a gate of the third transistor.