Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device

• US 9,024,700 B2
• Filed: 03/02/2009
• Issued: 05/05/2015
• Est. Priority Date: 02/28/2008
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Ranta, Tero Tapio
• Primary Examiner(s): Hoffberg, Robert J
• Assistant Examiner(s): DANG, HUNG Q
• Application Number:
  US12/735,954
• Publication Number:
  US 20110002080A1
• Time in Patent Office: 2,255 Days
• Field of Search: 361/277, 361/139, 257/303, 334/11, 334/14, 334/15, 331/36.R, 331/36.C, 327/554, 333/173, 333/174
• US Class Current: 333/17.3
• CPC Class Codes: H01F 21/12 discontinuously variable, e.g. tapped
• CPC Class Codes: H01G 4/002 Details
• CPC Class Codes: H01G 7/00 Capacitors in which the capacitance is varied by non-mechanical means; Processes of their manufacture
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H03H 11/28 Impedance matching networks
• CPC Class Codes: H03H 7/0153 Electrical filters; Controlling thereof
• CPC Class Codes: H03H 7/38 Impedance-matching networks
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 3/20 of single resonant circuit by varying inductance only or capacitance only
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03M 1/1061 using digitally programmable trimming circuits
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF− terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.

Claims

1. A digitally tuned capacitor (DTC) for use in an integrated circuit device, comprising:

(a) a first RF terminal;

(b) a second RF terminal;

(c) a control word input adapted to receive a digital control word having a selected plurality of b bits, wherein the plurality of b digital control word bits are ordered in significance from a least significant bit (LSB) to a most significant bit (MSB), and wherein the digital control word selectively controls a capacitance applied between the first and second RF terminals;

(d) a plurality of significant bit sub-circuits coupled in parallel between the first and second RF terminals, wherein the plurality of significant bit sub-circuits are ordered in significance from a least significant bit (LSB) sub-circuit to a most significant bit (MSB) sub-circuit, and wherein each significant bit sub-circuit is coupled to an associated and corresponding significant bit of the digital control word, in a one-to-one relationship, and wherein each significant bit sub-circuit comprises;

(i) at least one unit cell, wherein the unit cell comprises a plurality of stacked switches coupled in series with a capacitor;

wherein switching operation of the stacked switches is controlled by the associated and corresponding bit of the control word, and wherein the LSB sub-circuit comprises one unit cell, and each next significant bit sub-circuit comprises x times the number of instantiations of unit cells used in implementing its associated and corresponding previous less significant bit sub-circuit, wherein x is determined by a selected weighting coding scheme used to weight the sub-circuits, and wherein all of the unit cells of each sub-circuit are coupled together in parallel having a first node coupled to the first RF terminal and a second node coupled to the second RF terminal;

and wherein the digital control word selectively controls a capacitance applied between the first and second RF terminals by selectively controlling switching operation of the stacked switches, wherein capacitance applied between the first and second RF terminals by a selected sub-circuit is controlled by selectively turning ON stacked switches of the selected sub-circuit.

2. The DTC of claim 1, wherein the DTC is implemented in accordance with a binary weighting coding scheme, wherein x=2, and the LSB comprises a unit cell, each next significant bit sub-circuit comprises two times the number of instantiations of unit cells used in implementing its associated and corresponding previous less significant bit sub-circuit, and wherein the MSB sub-circuit comprises 2^b−

1 instantiations of unit cells coupled together in parallel between the first and second RF terminals.

3. The DTC of claim 1, wherein the DTC is implemented in accordance with a thermometer weighting coding scheme, and wherein the DTC comprises 2^b−

1 instantiations of unit cells coupled together in parallel between the first and second RF terminals.

4. The DTC of claim 1, wherein the unit cell comprises a stack of n FETs coupled together in series, and wherein the FET stack is further coupled in series to the capacitor, and wherein the capacitor comprises a MIM capacitor.

5. The DTC of claim 4, wherein the FET stack increases the power handling capability of the DTC, and wherein the number n of FETs used to implement the FET stack is adjusted in accordance with desired power handling requirements.

6. The DTC of claim 5, wherein the FET stack includes at least a bottom FET and a top FET, wherein the bottom FET has a first terminal coupled to the second RF terminal and a second terminal coupled to a next successive FET of the FET stack, and wherein the top FET is coupled to a first terminal of the MIM capacitor, and wherein a second terminal of the MIM capacitor is coupled to the first RF terminal.

7. The DTC of claim 6, wherein voltage division occurs between the MIM capacitor and the FET stack when the FET stack is turned OFF, wherein the FET stack has an actual height of n and an effective stack height of n_eff, and wherein the effective stack height exceeds the actual stack height due to the voltage division occurring between the MIM capacitor and the FET stack when the FET stack is turned OFF, and wherein the capacitance of the MIM capacitor can be selectively optimized to meet a desired power handling requirement.

8. The DTC of claim 7, wherein the effective stack height n_eff is determined in accordance with the following mathematical expression:

9. The DTC of claim 4, wherein the unit cell further comprises a plurality of gate resistors R_G having first terminals coupled to gates of associated and corresponding FETs of the FET stack and second terminals coupled to the associated and corresponding significant bit of the digital control word, and wherein the unit cell further comprises a plurality of drain-to-source resistors R_DS coupled across the drain and sources of each FET of the FET stack.

10. The DTC of claim 4, wherein the significant bit sub-circuits further comprise a plurality of gate resistors R_G having first terminals coupled to gates of associated and corresponding FETs of the FET stack and second terminals coupled to the associated and corresponding significant bit of the digital control word, and wherein the sub-circuits further comprise a plurality of drain-to-source resistors R_DS coupled across the drain and source of each FET of the FET stack, and wherein the resistance of the gate resistors R_G/2 of each next significant bit sub-circuit is 1/2 that of the resistance of the gate resistors R_G of its associated and corresponding previous less significant bit sub-circuit, and wherein the resistance of the drain-to-source resistors R_DS/2 of each next significant bit sub-circuit is 1/2 that of the resistance of the drain to source resistors R_DS of its associated and corresponding previous less significant bit sub-circuit.

11. The DTC of claim 10, wherein the integrated circuit die area occupied by the DTC of claim 10 is significantly less than the integrated circuit die area occupied by the DTC of claim 9.

12. The DTC of claim 3, wherein the thermometer weighting coding scheme results in the DTC having 2^b possible capacitance tuning states using 2^b−

1 identical unit cells, and wherein a capacitance differential between two adjacent capacitive tuning states of the control word are identical.

13. The DTC of claim 4, wherein a switching time of the FET stack is equal to R_G*C_GATE, wherein R_G comprises a gate resistance of the FET stack and C_GATE comprises a gate capacitance of the FET stack, and wherein the switching time is constant across all FETs of the DTC.

14. The DTC of claim 4, wherein the unit cell has a quality factor (Q), and wherein the Q-factor of the unit cell is dominated by a relationship between an ON resistance R_ON of the FET stack when the FET stack is turned ON and capacitance of the MIM capacitor (C_MIM), and wherein constant Q-factors are maintained across of all of the DTC sub-circuits because the relationship between R_ON and C_MIM remains constant across the entire DTC.

15. The DTC of claim 9, wherein the unit cell has a quality factor when the FET stack is turned ON (ON state Q-factor Q_ON) and a quality factor when the FET stack is turned OFF (OFF state Q-factor Q_OFF), and wherein Q_ON is proportional to 1/f, wherein f comprises a frequency of a signal applied to the DTC first and second RF terminals.

16. The DTC of claim 2 or 3, wherein the DTC is implemented in accordance with a combination of both binary weighting and thermometer weighting codes.

17. The DTC of claim 4, wherein n=1.

18. The DTC of claim 4, wherein the significance of the digital control word bits are arranged in ascending order from an LSB b₀ through an MSB b_b−

1.

19. The DTC of claim 4, wherein the significance of the digital control word bits are arranged in descending order from an MSB b_b−

1 through an LSB b₀.

20. The DTC of claim 4, wherein the unit cell FET stack has a width and is sized in accordance with a number y fingers of the FET stack, and wherein the width and number y of fingers are adjusted to provide a selected desirable size of the DTC.

21. The DTC of claim 4, wherein the MIM capacitor comprises one or more stacked capacitors, wherein the one or more stacked capacitors are selected to optimize the power handling capability of the DTC.

22. The DTC of claim 4, wherein the FETs comprise Accumulated Charge Control (ACC) SOI MOSFETs.

23. The DTC of claim 4, wherein the DTC is implemented using any of the following processing technologies:

gallium-arsenide (GaAs), Silicon-on-insulator (SOI), silicon-on-sapphire (SOS).

24. The DTC of claim 1, wherein the plurality of stacked switches comprise electro-Mechanical Systems (MEMS) switches.

25. The DTC of claim 4, wherein the digital control word bits selectively turn the FET stack ON by applying a selected positive voltage to the gates of the FETs in the FET stack, and wherein the bits turn the FET stack OFF by applying a selected negative voltage to the gates of the FETs in the FET stack.

26. The DTC of claim 4, wherein the digital control word bits selectively turn the FET stack ON by applying a selected positive voltage to the gates of the FETs in the FET stack, and wherein the bits turn the FET stack OFF by applying 0 volts to the gates of the FETs in the FET stack.

27. The DTC of claim 4, further including a fixed capacitor coupled in parallel between the first and second RF terminals.

28. The DTC of claim 27, wherein the included fixed capacitor is optimized to reduce an amount of integrated circuit die space required to implement the DTC.

29. The DTC of claim 27, wherein the included fixed capacitor is optimized to reduce a tuning ratio of the DTC.

30. The DTC of claim 4, wherein the DTC is implemented in an integrated circuit device, and wherein the integrated circuit device contains one or more additional DTCs as set forth in claim 4, and wherein one or more of the RF terminals are coupled together with one or more of the additional DTCs implemented in the integrated circuit device.

31. The DTC of claim 30, wherein the DTC is coupled with the one or more of the additional DTCs in a series configuration.

32. The DTC of claim 30, wherein the DTC is coupled with the one or more of the additional DTCs in a parallel configuration.

33. The DTC of claim 30, wherein the DTC is uncoupled and thereby isolated from the one or more additional DTCs contained in the integrated circuit device.

53. The DTC of any preceding claim, wherein the unit cell comprises a stack of n FETs coupled together in series, and wherein the FET stack is further coupled in series to the one or more capacitors.

54. The DTC of claim 53, wherein the capacitance of the one or more capacitors can be selectively optimized to meet a desired power handling requirement.

55. The DTC of claim 53, wherein the unit cell further comprises a plurality of gate resistors R_G having first terminals coupled to gates of associated and corresponding FETs of the FET stack and second terminals coupled to the associated and corresponding control word bit, and wherein the unit cell further comprises a plurality of drain-to-source resistors R_DS coupled across the drain and sources of each FET of the FET stack.

56. The DTC of claim 53, wherein the sub-circuits further comprise a plurality of gate resistors R_G scaled in inverse proportion to the number of parallel unit cells, and wherein the sub-circuits further comprise a plurality of drain-to-source resistors R_DS scaled in inverse proportion to the number of parallel unit cells.

57. The DTC of claim 53, wherein the switching time of the FET stack is constant across all FETs of the DTC.

58. The DTC of claim 53, wherein the unit cell has a quality factor Q, and wherein constant Q-factors are maintained across all of the DTC sub-circuits.

59. The DTC of claim 53, wherein the unit cell has a quality factor Q, and wherein constant Q-factors are maintained across of all of the DTC sub-circuits.

61. The DTC of claim 53, wherein the unit cell FET stack has a width and is sized in accordance with a number y of fingers of the FET stack, and wherein the width and number y of fingers are adjusted to provide a selected desirable size of the DTC.

62. The DTC of claim 53, wherein the one or more stacked capacitors are selected to optimize the power handling capability of the DTC.

63. The DTC of claim 53, wherein the FETs comprise Accumulated Charge Control (ACC) SOI MOSFETs.

64. The DTC of claim 53, wherein the one or more capacitors are integrated on an integrated circuit die wherein the DTC is implemented.

65. The DTC of claim 53, wherein the DTC is implemented using any of the following processing technologies:

gallium-arsenide (GaAs), Silicon-on-insulator (SOI), silicon-on-sapphire (SOS).

68. The DTC of claim 53, wherein the MIM capacitor is integrated on an integrated circuit die wherein the DTC is implemented.

69. The DTC of claim 53, wherein the control word bits selectively turn the FET stack ON by applying a selected positive voltage to the gates of the FETs in the FET stack, and wherein the bits turn the FET stack OFF by applying a selected negative voltage to the gates of the FETs in the FET stack.

70. The DTC of claim 53, wherein the control word bits selectively turn the FET stack ON by applying a selected positive voltage to the gates of the FETs in the FET stack, and wherein the bits turn the FET stack OFF by applying 0 volts to the gates of the FETs in the FET stack.

71. The DTC of claim 53, further including one or more capacitors coupled in parallel between the first and second RF terminals.

72. The DTC of claim 71, wherein the included one or more capacitors are optimized to reduce an amount of integrated circuit die space required to implement the DTC.

73. The DTC of claim 71, wherein the included one or more capacitors are optimized to set a tuning ratio of the DTC.

74. The DTC of claim 53, wherein the DTC is implemented in an integrated circuit device, and wherein the integrated circuit device contains one or more additional DTCs.

75. The DTC of claim 74, wherein the DTC is coupled with the one or more of the additional DTCs in a series or parallel configuration.

76. The DTC of claim 75, wherein the DTC is uncoupled and thereby isolated from the one or more additional DTCs contained in the integrated circuit device.

83. The DTC of any preceding claim, wherein the unit cell comprises a stack of n FETs coupled together in series, and wherein the FET stack is further coupled in series to the one or more capacitors.

84. The DTC of claim 83, wherein the capacitance of the one or more capacitors can be selectively optimized to meet a desired power handling requirement.

85. The DTC of claim 83, wherein the unit cell further comprises a plurality of gate resistors R_G having first terminals coupled to gates of associated and corresponding FETs of the FET stack and second terminals coupled to the associated and corresponding control word bit, and wherein the unit cell further comprises a plurality of drain-to-source resistors R_DS coupled across the drain and sources of each FET of the FET stack.

86. The DTC of claim 83, wherein the sub-circuits further comprise a plurality of gate resistors R_G scaled in inverse proportion to the number of parallel unit cells, and wherein the sub-circuits further comprise a plurality of drain-to-source resistors R_DS scaled in inverse proportion to the number of parallel unit cells.

87. The DTC of claim 83, wherein the switching time of the FET stack is constant across all FETs of the DTC.

88. The DTC of claim 83, wherein the unit cell has a quality factor Q, and wherein constant Q-factors are maintained across of all of the DTC sub-circuits, stack R_G comprises a gate resistance of the FET stack and R_ON comprises an on-resistance of the FET stack when it is turned ON.

90. The DTC of claim 83, wherein the unit cell FET stack has a width and is sized in accordance with a number y of fingers of the FET stack, and wherein the width and number y of fingers are adjusted to provide a selected desirable size of the DTC.

91. The DTC of claim 83, wherein the one or more stacked capacitors are selected to optimize the power handling capability of the DTC.

92. The DTC of claim 83, wherein the FETs comprise Accumulated Charge Control, ACC, SOI MOSFETs.

93. The DTC of claim 83, wherein the one or more capacitors are integrated on an integrated circuit die wherein the DTC is implemented.

94. The DTC of claim 83, wherein the digital control word bits selectively turn the FET stack ON by applying a selected positive voltage to the gates of the FETs in the FET stack, and wherein the bits turn the FET stack OFF by applying a selected negative voltage to the gates of the FETs in the FET stack.

95. The DTC of claim 83, wherein the digital control word bits selectively turn the FET stack ON by applying a selected positive voltage to the gates of the FETs in the FET stack, and wherein the bits turn the FET stack OFF by applying 0 volts to the gates of the FETs in the FET stack.

96. The DTC of claim 83, further including one or more capacitors coupled in parallel between the first and second RF terminals.

97. The DTC of claim 96, wherein the included one or more capacitors are optimized to reduce an amount of integrated circuit die space required to implement the DTC.

98. The DTC of claim 96, wherein the included one or more capacitors are optimized to set a tuning ratio of the DTC.

99. The DTC of claim 83, wherein the DTC is implemented in an integrated circuit device, and wherein the integrated circuit device contains one or more additional DTCs.

100. The DTC of claim 99, wherein the DTC is coupled with the one or more of the additional DTCs in a series or parallel configuration.

101. The DTC of claim 100, wherein the DTC is uncoupled and thereby isolated from the one or more additional DTCs contained in the integrated circuit device.

34. A digitally tuned capacitor (DTC) for use in an integrated circuit device, comprising:

(a) a first RF terminal;

(b) a second RF terminal;

(c) a control word input adapted to receive a digital control word having a selected plurality of b bits, wherein the plurality of b digital control word bits are ordered in significance from a least significant bit (LSB) to a most significant bit (MSB), and wherein the digital control word selectively controls a capacitance applied between the first and second RF terminals;

(d) a plurality of significant bit sub-circuits coupled in parallel between the first and second RF terminals, wherein the plurality of significant bit sub-circuits are ordered in significance from a least significant bit (LSB) sub-circuit to a most significant bit (MSB) sub-circuit, and wherein each significant bit sub-circuit is coupled to an associated and corresponding significant bit of the digital control word, in a one-to-one relationship, and wherein each significant bit sub-circuit comprises at least one unit cell and wherein the digital control word selectively controls a capacitance applied between the first and second RF terminals by selectively controlling switching operation of the significant bit sub-circuits.

35. The DTC of claim 34, wherein the DTC is implemented in accordance with a binary weighting coding scheme, wherein x=2, and the LSB comprises a unit cell, each next significant bit sub-circuit comprises two times the number of instantiations of unit cells used in implementing its associated and corresponding previous less significant bit sub-circuit, and wherein the MSB sub-circuit comprises 2^b−

1 instantiations of unit cells coupled together in parallel between the first and second RF terminals.

36. The DTC of claim 34, wherein the DTC is implemented in accordance with a thermometer weighting coding scheme, and wherein the DTC comprises 2^b−

1 instantiations of unit cells coupled together in parallel between the first and second RF terminals.

37. The DTC of claim 36, wherein the thermometer weighting coding scheme results in the DTC having 2^b possible capacitance tuning states using 2^b−

1 identical unit cells, and wherein a capacitance differential between two adjacent capacitive tuning states of the control word are identical.

38. The DTC of claim 34, wherein the unit cell has a quality factor (Q), and wherein the Q-factor of the unit cell is dominated by a relationship between an ON resistance R_ON of a FET stack when the FET stack is turned ON and capacitance of a MIM capacitor (C_MIM), and wherein constant Q-factors are maintained across of all of the sub-circuits because the relationship between R_ON and C_MIM remains constant across the entire DTC.

39. The DTC of claim 35, wherein the DTC is implemented in accordance with a combination of both binary weighting and thermometer weighting codes.

40. The DTC of claim 34, wherein the unit cell comprises a stack of n FETs coupled together in series, and wherein the FET stack is further coupled in series to the capacitor, and wherein the capacitor comprises a MIM capacitor.

41. The DTC of claim 40, wherein the significance of the digital control word bits are arranged in ascending order from an LSB b₀ through an MSB b_b−

1.

42. The DTC of claim 40, wherein the significance of the digital control word bits are arranged in descending order from an MSB b_b−

1 through an LSB b₀.

43. The DTC of claim 40, wherein the FETs comprise Accumulated Charge Control (ACC) SOI MOSFETs.

44. The DTC of claim 34, wherein the DTC is implemented using any of the following processing technologies:

gallium-arsenide (GaAs), Silicon-on-insulator (SOI), silicon-on-sapphire (SOS).

45. The DTC of claim 40, wherein the plurality of stacked FETs comprise electro-Mechanical Systems (MEMS) switches.

46. The DTC of claim 40, wherein the MIM capacitor is integrated on an integrated circuit die wherein the DTC is implemented.

47. The DTC of claim 40, wherein the DTC is implemented in an integrated circuit device, and wherein the integrated circuit device contains one or more additional DTCs as set forth in claim 40, and wherein one or more of the RF terminals are coupled together with one or more of the additional DTCs implemented in the integrated circuit device.

48. The DTC of claim 47, wherein the DTC is coupled with the one or more of the additional DTCs in a series configuration.

49. A digitally tuned capacitor, DTC, for use in an integrated circuit device, comprising:

(a) a first RF terminal;

(b) a second RF terminal;

(c) an input means receiving a control word having a selected plurality of b control word bits, wherein the control word selectively controls a capacitance applied between the first and second RF terminals;

(d) a plurality of sub-circuits coupled in parallel between the first and second RF terminals, wherein each sub-circuit is coupled to an associated and corresponding control word bit, in a one-to-one relationship, and wherein each sub-circuit comprises;

at least one unit cell, wherein the unit cell comprises a plurality of stacked switches coupled in series with one or more capacitors;

wherein switching operation of the stacked switches is controlled by the associated and corresponding control word bit, and wherein the LSB sub-circuit comprises one unit cell, and each additional sub-circuit comprises a number of unit cells used in implementing its associated and corresponding sub-circuit, wherein all of the unit cells of each sub-circuit are coupled together in parallel having a first node coupled to the first RF terminal and a second node coupled to the second RF terminal;

and wherein the control word selectively controls the capacitance applied between the first and second RF terminals by selectively controlling switching operation of the significant bit sub-circuits, wherein the capacitance applied between the first and second RF terminals by a selected sub-circuit is controlled by selectively turning ON stacked switches of the selected sub-circuit.

50. The DTC of claim 49, wherein the second RF terminal is ground.

51. The DTC of claim 49, wherein the DTC is implemented in accordance with a binary weighting coding scheme.

52. The DTC of claim 49, wherein the DTC is implemented in accordance with a thermometer weighting coding scheme.

60. The DTC of claim 51 or 52, wherein the DTC is implemented in accordance with a combination of binary weighting and thermometer weighting codes.

66. The DTC of claim 49, wherein the plurality of stacked switches comprise electro-Mechanical Systems (MEMS) switches.

67. The DTC of claim 49, wherein the plurality of stacked switches comprise laterally diffused metal oxide semiconductor (LDMOS) transistors.

77. A digitally tuned capacitor, DTC, for use in an integrated circuit device, comprising:

(a) a first RF terminal;

(b) a second RF terminal;

(c) an input means receiving a digital control word having a selected plurality of b digital control word bits, wherein the digital control word selectively controls a capacitance applied between the first and second RF terminals;

(d) a plurality of sub-circuits coupled in parallel between the first and second RF terminals wherein each sub-circuit is coupled to an associated and corresponding control word bit, in a one-to-one relationship, and wherein each sub-circuit comprises;

at least one unit cell, wherein the unit cell comprises a plurality of stacked switches coupled in series with one or more capacitors;

wherein switching operation of the stacked switches is controlled by the associated and corresponding digital control word bit, and wherein the LSB sub-circuit comprises one unit cell, and each additional sub-circuit comprises a number of unit cells used in implementing its associated and corresponding sub-circuit, wherein all of the unit cells of each sub-circuit are coupled together in parallel having a first node coupled to the first RF terminal and a second node coupled to the second RF terminal;

and wherein the digital control word selectively controls the capacitance applied between the first and second RF terminals by selectively controlling switching operation of the significant bit sub-circuits, wherein the capacitance applied between the first and second RF terminals by a selected sub-circuit is controlled by selectively turning ON stacked switches of the selected sub-circuit.

78. The DTC of claim 77, wherein the second RF terminal is ground.

79. A digitally tuned capacitor, DTC, for use in an integrated circuit device, comprising:

(a) a first RF terminal;

(b) a second RF terminal;

(c) an input means receiving a digital control word having a selected plurality of b digital control word bits, wherein the digital control word selectively controls a capacitance applied between the first and second RF terminals;

(d) a plurality of sub-circuits coupled in parallel between the first and second RF terminals, wherein each sub-circuit is coupled to an associated and corresponding control word bit, in a one-to-one relationship, and wherein each sub-circuit comprises;

at least one unit cell, wherein the unit cell comprises a plurality of stacked switches coupled in series with one or more capacitors;

wherein switching operation of the stacked switches is controlled by the associated and corresponding digital control word bit, and wherein the LSB sub-circuit comprises one unit cell, and each additional sub-circuit comprises a number of unit cells used in implementing its associated and corresponding sub-circuit, wherein all of the unit cells of each sub-circuit are coupled together in parallel having a first node coupled to the first RF terminal and a second node coupled to the second RF terminal;

and wherein the digital control word selectively controls the capacitance applied between the first and second RF terminals by selectively controlling switching operation of the significant bit sub-circuits, wherein the capacitance applied between the first and second RF terminals by a selected sub-circuit is controlled by selectively turning ON stacked switches of the selected sub-circuit.

80. The DTC of claim 79, wherein the second RF terminal is grounded.

81. The DTC of claim 79, wherein the DTC is implemented in accordance with a binary weighting coding scheme.

82. The DTC of claim 79, wherein the DTC is implemented in accordance with a thermometer weighting coding scheme.

89. The DTC of claim 81 or 82, wherein the DTC is implemented in accordance with a combination of binary weighting and thermometer weighting codes.

102. A method of digitally tuning a capacitor in an integrated circuit device, comprising:

(a) establishing electrical communication with a first RF terminal;

(b) establishing electrical communication with a second RF terminal;

(c) receiving a digital control having a selected plurality of b digital control bits; and

(d) selectively controlling a capacitance applied between the first and second RF terminals;

wherein the capacitance applied between the first and second RF terminals is controlled by coupling a plurality of sub-circuits in parallel between the first and second RF terminals, and wherein each sub-circuit is coupled to an associated and corresponding control bit, and wherein each sub-circuit comprises at least one unit cell, wherein the unit cell comprises a plurality of stacked switches coupled in series with one or more capacitors;

wherein switching operation of the stacked switches is controlled by the associated and corresponding control bit, and wherein the LSB sub-circuit comprises one unit cell, and each additional sub-circuit comprises a number of unit cells used in implementing its associated and corresponding sub-circuit, and wherein all of the unit cells of each sub-circuit are coupled together in parallel having a first node coupled to the first RF terminal and a second node coupled to the second RF terminal; and

wherein the digital control selectively controls the capacitance applied between the first and second RF terminals by selectively controlling switching operation of the stacked switches, wherein the capacitance applied between the first and second RF terminals by a selected sub-circuit is controlled by selectively turning ON stacked switches of the selected sub-circuit.

103. The method of claim 102, wherein the second RF terminal is grounded.

104. A digitally tuned capacitor, DTC, for use in an integrated circuit device, comprising:

(a) a first RF terminal;

(b) a second RF terminal;

(c) an input means receiving a control word having a selected plurality of b control word bit, wherein the control word selectively controls a capacitance applied between the first and second RF terminals;

(d) a plurality of sub-circuits coupled in parallel between the first and second RF terminals, wherein each sub-circuit is coupled to an associated and corresponding control word bit, in a one-to-one relationship, and wherein each sub-circuit comprises;

at least one unit cell, wherein the unit cell comprises a plurality of stacked switches coupled in series with one or more capacitors;

wherein switching operation of the stacked switches is controlled by the associated and corresponding control word bit, and wherein the LSB sub-circuit comprises one unit cell, and each additional sub-circuit comprises a number of unit cells used in implementing its associated and corresponding sub-circuit, wherein all of the unit cells of each sub-circuit are coupled together in parallel having a first node coupled to the first RF terminal and a second node coupled to the second RF terminal;

and wherein the control word selectively controls the capacitance applied between the first and second RF terminals by selectively controlling switching operation of the significant bit sub-circuits, wherein the capacitance applied between the first and second RF terminals by a selected sub-circuit is controlled by selectively turning ON stacked switches of the selected sub-circuit.

105. The DTC of claim 104, wherein the second RF terminal is grounded.

106. The DTC of claim 104, wherein the DTC is implemented in accordance with a binary weighting coding scheme.

107. The DTC of claim 104, wherein the DTC is implemented in accordance with a thermometer weighting coding scheme.

108. The DTC of claim 104, 105, 106, or 107, wherein the unit cell comprises a stack of n FETs coupled together in series, and wherein the FET stack is further coupled in series to the one or more capacitors.

109. The DTC of claim 108, wherein the capacitance of the one or more capacitors can be selectively optimized to meet a desired power handling requirement.

110. The DTC of claim 108, wherein the unit cell further comprises a plurality of gate resistors R_G having first terminals coupled to gates of associated and corresponding FETs of the FET stack and second terminals coupled to the associated and corresponding control word bit, and wherein the unit cell further comprises a plurality of drain-to-source resistors R_DS coupled across the drain and sources of each FET of the FET stack.

111. The DTC of claim 108, wherein the sub-circuits further comprise a plurality of gate resistors R_G scaled in inverse proportion to the number of parallel unit cells, and wherein the sub-circuits further comprise a plurality of drain-to-source resistors R_DS scaled in inverse proportion to the number of parallel unit cells.

112. The DTC of claim 108, wherein the switching time of the FET stack is constant across all FETs of the DTC.

113. The DTC of claim 108, wherein the unit cell has a quality factor Q, and wherein constant Q-factors are maintained across all of the DTC sub-circuits.

114. The DTC of claim 108, wherein the unit cell has a quality factor Q, and wherein constant Q-factors are maintained across of all of the DTC sub-circuits.

115. The DTC of claim 106 or 107, wherein the DTC is implemented in accordance with a combination of binary weighting and thermometer weighting codes.

116. The DTC of claim 108, wherein the unit cell FET stack has a width and is sized in accordance with a number y of fingers of the FET stack, and wherein the width and number y of fingers are adjusted to provide a selected desirable size of the DTC.

117. The DTC of claim 108, wherein the one or more stacked capacitors are selected to optimize the power handling capability of the DTC.

118. The DTC of claim 108, wherein the FETs comprise Accumulated Charge Control (ACC) SOI MOSFETs.

119. The DTC of claim 108, wherein the one or more capacitors are integrated on an integrated circuit die wherein the DTC is implemented.

120. The DTC of claim 108, wherein the DTC is implemented using any of the following processing technologies:

gallium-arsenide (GaAs), Silicon-on-insulator (SOI), silicon-on-sapphire (SOS).

121. The DTC of claim 104, wherein the plurality of stacked switches comprise electro-Mechanical Systems (MEMS) switches.

122. The DTC of claim 104, wherein the plurality of stacked switches comprise laterally diffused metal oxide semiconductor (LDMOS) transistors.

123. The DTC of claim 108, wherein MIM capacitor is integrated on an integrated circuit die wherein the DTC is implemented.

124. The DTC of claim 108, wherein the control word bits selectively turn the FET stack ON by applying a selected positive voltage to the gates of the FETs in the FET stack, and wherein the bits turn the FET stack OFF by applying a selected negative voltage to the gates of the FETs in the FET stack.

125. The DTC of claim 108, wherein the control word bits selectively turn the FET stack ON by applying a selected positive voltage to the gates of the FETs in the FET stack, and wherein the bits turn the FET stack OFF by applying 0 volts to the gates of the FETs in the FET stack.

126. The DTC of claim 108, further including one or more capacitors coupled in parallel between the first and second RF terminals.

127. The DTC of claim 126, wherein the included one or more capacitors are optimized to reduce an amount of integrated circuit die space required to implement the DTC.

128. The DTC of claim 126, wherein the included one or more capacitors are optimized to set a tuning ratio of the DTC.

129. The DTC of claim 108, wherein the DTC is implemented in an integrated circuit device, and wherein the integrated circuit device contains one or more additional DTCs.

130. The DTC of claim 129, wherein the DTC is coupled with the one or more of the additional DTCs in a series or parallel configuration.

131. The DTC of claim 130, wherein the DTC is uncoupled and thereby isolated from the one or more additional DTCs contained in the integrated circuit device.

132. A digitally tuned capacitor, DTC, for use in an integrated circuit device, comprising:

(a) a first RF terminal;

(b) a second RF terminal;

(c) an input means receiving a digital control word having a selected plurality of b digital control word bits, wherein the digital control word selectively controls a capacitance applied between the first and second RF terminals;

(d) a plurality of sub-circuits coupled in parallel between the first and second RF terminals, wherein each sub-circuit is coupled to an associated and corresponding control word bit, in a one-to-one relationship, and wherein each sub-circuit comprises;

at least one unit cell, wherein the unit cell comprises a plurality of stacked switches coupled in series with one or more capacitors;

wherein switching operation of the stacked switches is controlled by the associated and corresponding digital control word bit, and wherein the LSB sub-circuit comprises one unit cell, and each additional sub-circuit comprises a number of unit cells used in implementing its associated and corresponding sub-circuit, wherein all of the unit cells of each sub-circuit are coupled together in parallel having a first node coupled to the first RF terminal and a second node coupled to the second RF terminal;

and wherein the digital control word selectively controls the capacitance applied between the first and second RF terminal by selectively controlling switching operation of the significant bit sub-circuits, wherein the capacitance applied between the first and second RF terminals by a selected sub-circuit is controlled by selectively turning ON stacked switches of the selected sub-circuit.

133. The DTC of claim 132, wherein the second RF terminal is grounded.

134. A method of digitally tuning a capacitor in an integrated circuit device, comprising:

(a) establishing electrical communication with a first RF terminal;

(b) establishing electrical communication with a second RF terminal;

(c) receiving a digital control word having a selected plurality of b bits, wherein the plurality of b digital control word bits are ordered in significance from a least significant bit (LSB) to a most significant bit (MSB); and

(d) selectively controlling a capacitance applied between the first and second RF terminals;

wherein the capacitance applied between the first and second RF terminals is controlled by coupling a plurality of significant bit sub-circuits in parallel between the first and second RF terminals,

and wherein the plurality of significant bit sub-circuits are ordered in significance from a least significant bit (LSB) sub-circuit to a most significant bit (MSB) sub-circuit, and wherein each significant bit sub-circuit is coupled to an associated and corresponding significant bit of the digital control word, in a one-to-one relationship, and wherein each significant bit sub-circuit comprises at least one unit cell, wherein the unit cell comprises a plurality of stacked switches coupled in series with a capacitor;

wherein switching operation of the stacked switches is controlled by the associated and corresponding bit of the control word, and wherein the LSB sub-circuit comprises one unit cell, and each next significant bit sub-circuit comprises x times the number of instantiations of unit cells used in implementing its associated and corresponding previous less significant bit sub-circuit, wherein x is determined by a selected weighting coding scheme used to weight the sub-circuits, and wherein all of the unit cells of each sub-circuit are coupled together in parallel having a first node coupled to the first RF terminal and a second node coupled to the second RF terminal; and

wherein the digital control word selectively controls a capacitance applied between the first and second RF terminals by selectively controlling switching operation of the stacked switches, wherein capacitance applied between the first and second RF terminals by a selected sub-circuit is controlled by selectively turning ON stacked switches of the selected sub-circuit.